PACE1750A
SIGNAL PROPAGATION DELAYS1,2
15 MHz
20 MHz
30 MHz
40 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Symbol
tC(BR)L
tC(BR)H
tBGV(C)
tC(BG)X
tC(BB)L
tC(BB)H
tBBV(C)
tC(BB)X
tC(BL)L
Parameter
Unit
BUS REQ
BUS REQ
BUS GNT
BUS GNT
45
45
33
33
25
25
22
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
setup
hold
5
5
5
5
5
5
5
5
LOW
BUS BUSY
BUS BUSY
BUS BUSY
BUS BUSY
BUS LOCK
BUS LOCK
BUS LOCK
BUS LOCK
35
35
25
25
24
20
20
15
HIGH
setup
hold
5
5
5
5
5
5
5
5
LOW
HIGH
setup
hold
50
50
30
30
25
25
21
17
tC(BL)H
tBLV(C)
tC(BL)X (IN)
tC(ST)V
tC(ST)V
5
5
5
5
5
5
5
5
M/ , R/ Status
IO W
45
40
30
25
25
20
20
20
AS0-AS3, AK0-AK3, D/I Status
AS0-AS3, AK0-AK3, D/I Status,
M/ , R/
tC(ST)X
0
0
0
0
ns
IO
W
STRBA HIGH
25
25
22
22
17
17
16
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC(SA)H
tC(SA)L
tSAL(IBA)X
tRAV(C)
STRBA LOW
Address hold from STRBA LOW
RDYA setup
5
5
5
5
5
5
5
5
5
5
5
5
RDYA hold
tC(RA)X
LOW write
STRBD
25
25
25
22
22
22
17
17
17
14
14
14
tC(SDW)L
tC(SD)H
HIGH
STRBD
LOW read
STRBD
tFC(SDR)L
tSDRH(IBD)X
tSDWH(IBD)X
tSDL(SD)H
tRDV(C)
HIGH
STRBD
0
45
50
5
0
30
40
5
0
25
35
5
0
17
20
5
HIGH
STRBD
write
STRBD
RDYD setup
RDYD hold
5
5
5
5
tC(RD)X
IB0-IB15
45
30
25
20
tC(IBA)V
IB0-IB15
0
5
8
0
0
5
7
0
0
5
6
0
0
5
5
0
tFC(IBA)X
tIBDRV(C)
tC(IBD)X
IB0-IB15 setup
IB0-IB15 hold (read)
Data valid out (write)
tC(IBD)X
Do c um e nt # MICRO-3 Re v. C
Pa g e 4 o f 24
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
