AND1741MST
Intelligent Graphics Display
Power Supply
Timing Relationships and Diagram
Signal Timing Relationships
LCD panel is driven by the voltage VDD–VEE, so adjustable
V
EE is required for contrast control and temperature
Item
C/D Set Up Time
C/D Hold Time
Symbol
tCDS
Min.
100
10
Max.
Unit
compensation.
–
–
Temperature Variations
tCDH
Temperature
0°C
VDD–VEE (MST)
21.0
VDD–VEE (BST)
20.0
CE, RD, WR
tCE RD,tWR
t
80
–
Pulse Width
ns
+25°C
+50°C
19.5
17.6
18.5
16.6
tDS
tDH
tACC
tOH
Data Set Up Time
Data Hold Time
Access Time
80
40
–
–
–
150
50
Output Hold Time
10
Timing Diagram
C/D
tCDH
tCDS
tCP,tRD,tWP
tDS
CE
RD, WR
D0-D7
(WRITE)
tDH
tOH
D0-D7
(READ)
tACC
Block Diagram
Because signal lines are directly connected
to C-MOS and are not pull-up or pull-down
internally, except RESET which is pull-up to
8
8
D0-D7
I/O0-I/O7
D0-D7
V
DD, you must guard all signals from
13
WR
RD
CE
C/D
RESET
external noise.
AD0-AD12
T6963C
A0-A12
R/W
CE1
RAM
(8K byte)
ED
X-Driver
80
X-Driver
80
X-Driver
80
HSCP
FR
Control Lines
LP
CDATA
64
64
Y-Driver
Y-Driver
LCD
VFL
VFL
Backlight
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085
Tel:408.523.8200 • Fax:408.733.1287 • sales@purdyelectronics.com • www.purdyelectronics.com
3
7/20/07
PURDY [ PURDY ELECTRONICS CORPORATION ]
