AND1741MST/BST
Intelligent Graphics Display
Power Supply
Timing Relationships and Diagram
Signal Timing Relationships
LCD panel is driven by the voltage VDD–VEE, so adjustable
VEE is required for contrast control and temperature
Item
C/D Set Up Time
C/D Hold Time
Symbol
Min.
100
10
Max.
Unit
compensation.
tCDS
–
–
Temperature Variations
tCDH
Temperature
0°C
VDD–VEE (MST)
21.0
VDD–VEE (BST)
20.0
CE, RD, WR
Pulse Width
tCEtRD,tWR
80
–
ns
+25°C
19.5
18.5
tDS
tDH
tACC
tOH
Data Set Up Time
Data Hold Time
Access Time
80
40
–
–
–
+50°C
17.6
16.6
150
50
Output Hold Time
10
Timing Diagram
C/D
tCDH
tCDS
CE
tCP,tRD,tWP
RD, WR
tDS
D0-D7
(WRITE)
tDH
D0-D7
(READ)
tACC
tOH
Block Diagram
Because signal lines are directly connected
to C-MOS and are not pull-up or pull-down
internally, except RESET which is pull-up to
VDD, you must guard all signals from
external noise.
8
8
D0-D7
I/O0-I/O7
D0-D7
13
WR
RD
AD0-AD12
T6963C
A0-A12
R/W
CE1
RAM
(8K byte)
CE
C/D
ED
RESET
X-Driver
80
X-Driver
80
X-Driver
80
HSCP
FR
LP
Control Lines
CDATA
64
64
Y-Driver
Y-Driver
LCD
VFL
VFL
Backlight
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94086
Tel:408.523.8200 • Fax:408.733.1287 • email@purdyelectronics.com • www.purdyelectronics.com
3-24
9/8/98
PURDY [ PURDY ELECTRONICS CORPORATION ]
