AND1013ST-30/-EO
Intelligent Graphics Display
Block Diagram
Because signal lines are directly connected
to C-MOS and are not pull-up or pull-down
internally, except RESET which is pull-up to
VDD, you must guard all signals from
external noise.
8
8
D0-D7
I/O0-I/O7
RAM
D0-D7
12
A0-A11
AD0-AD12
R/W
CE
R/W
CE1
WR
RD
T6963C
CE
X-Driver
80
X-Driver
80
C/D
HSCP
FR
RESET
HALT
Control Lines
LP
CDATA
64
64
Y-Driver
Y-Driver
LCD
Dimensional Outline
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94086
Tel:408.523.8200 • Fax:408.733.1287 • email@purdyelectronics.com • www.purdyelectronics.com
7/8/98
3-15
PURDY [ PURDY ELECTRONICS CORPORATION ]
