Octoberr 2003
rev 1.0
ASM3P1819A-H
Block Diagram
SRS
D_C PD#
Modulation
VDD
PLL
XIN
Crystal
Oscillator
Frequency
Divider
Output
Phase
Loop
VCO
XOUT
Divider
Detector
Filter
Feedback
Divider
ModOUT
REF
VSS
Pin Diagram
XIN
1
2
3
4
8
7
6
5
XOUT
XIN
VSS
1
2
3
4
8
7
6
5
XOUT
VSS
VDD
PD#
VDD
PD#
SRS
D_C
REF
REF
ModOUT
ModOUT
ASM3P1819A-D
Pin Name
ASM3P1819E-H
Pin Description
Pin#
Type
Description
ASM3P1819A-D
ASM3P1819E-H
1
2
XIN
VSS
XIN
VSS
I
P
Connect to externally generated clock signal or crystal.
Ground to entire chip.
Digital logic input used to select Down (LOW) or Center
(HIGH) spread options (Refer Spread Deviation
Selection Table.) This pin has an internal pull-up
resistor.
3
D_C
I
Spread range select. Digital logic input used to select
frequency deviation (Refer Spread Deviation Selection
Table.)
3
SRS
I
4
5
ModOUT
REF
ModOUT
REF
O
O
Spread spectrum clock output.
Un-modulated reference output clock of the input
frequency.
Power-Down control pin. Pull LOW to enable Power-
Down mode. This pin has an internal pull-up resistor.
6
7
8
PD#
VDD
PD#
REF
I
P
O
Connect to +3.3V.
Crystal connection. If connected to an externally
XOUT
XOUT
generated clock, this pin must be left unconnected.
Low EMI Clock for Mobile VGA
2 of 8
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
