May 2005
ASM2I99448
rev 0.3
Table 8. AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to +85°C)1
Symbol
fref
Characteristics
Min
0
0
400
1.2
1.4
Typ
Max
350
350
1000
VCC-0.8
Unit
MHz
MHz
mV
V
Condition
Input Frequency
fMAX
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
VPP
VCMR
PCLK
PCLK
LVPECL
LVPECL
2
tP, REF
tr, tf
tPLH/HL
tPLH/HL
tPLZ, HZ
tPZL, LZ
nS
nS
1.03
0.8 to 2.0V
PCLK to any Q
CCLK to any Q
1.5
1.7
4.2
nS
4.4
nS
Output Disable Time
Output Enable Time
11
11
nS
nS
0.0
0.0
1.0
1.5
nS
nS
nS
nS
CCLK to CLK_STOP
PCLK to CLK_STOP
CCLK to CLK_STOP
PCLK to CLK_STOP
tS
Setup time
tH
Hold time
tsk(O)
tsk(PP)
Output-to-output Skew
Device-to-device Skew
Output pulse skew4
150
2.7
pS
nS
PCLK or CCLK to any Q
Using CCLK Using PCLK
200
pS
tSK(p)
300
pS
fQ< 350 MHz and using CLK
fQ<200 MHz and using PCLK
45
45
0.1
50
50
55
55
1.0
%
%
nS
DCQ
tr, tf
Output Duty Cycle
DCREF = 50%
0.6 to 1.8V
Output Rise/Fall Time
Note: 1. AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP)
.
3. Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference
input pulse width, output duty cycle and maximum frequency specifications.
4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
6 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
