January 2006
rev 0.2
ASM2P20807A
2.5V
1.25V
INPUT
OV
tPLH
tPLHL 1
VOH
1.25 V
OUTPUT 1
VOL
tSK(O)
tSK(O)
VOH
1.25 V
OUTPUT 2
VOL
tPHL2
tPLH2
tSK(O) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1
]
Output Skew - tSK(O)
2.5V
1.25V
INPUT
OV
tPLH 1
tPLHL
1
VOH
1.25 V
DEVICE 1 OUTPUT
DEVICE 2 OUTPUT
VOL
tSK(t)
tSK(t)
VOH
1.25 V
VOL
tPHL2
tSK(t) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1
tPLH2
DEVICE 2 OUTPUT
]
Part-to-Part Skew - tSK(PP)
NOTE: Device 1 and device 2 are same package type and speed grade.
Test Conditions
Symbol
CL
VCC = 2.5V ±0.2V
Unit
221
pF
122
RT
Z OUT of pulse generator
Ω
tR / tF
1.251
1.22
nS
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
t
R / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
NOTES:
1. Test conditions at 100MHz.
2. Test conditions at 150MHz.
2.5V CMOS 1-TO-10 CLOCK DRIVER
7 of 12
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
