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ASM1832SF 参数 Datasheet PDF下载

ASM1832SF图片预览
型号: ASM1832SF
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V微处理器电源监控和复位电路 [3.3V μP Power Supply Monitor and Reset Circuit]
分类和应用: 电源电路电源管理电路微处理器复位电路光电二极管监控输入元件
文件页数/大小: 9 页 / 198 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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October 2006  
rev 1.6  
ASM1832  
signals. The pushbutton input is debounced and is pulled  
minimum timeout period, reset signals become active. On  
power-up after the supply voltage returns to an in-tolerance  
condition, the reset signal remains active for 250ms  
minimum, allowing the power supply and system  
microprocessor to stabilize.  
HIGH through an internal 40kresistor.  
When PBRST is held LOW for the minimum time tPB, both  
resets become active and remain active for a minimum time  
period of 250ms after PBRST returns HIGH.  
ST Pulses as short as 20ns can be detected.  
The debounced input is guaranteed to recognize pulses  
greater than 20ms. No external pull-up resistor is required,  
since PBRST is pulled HIGH by an internal 40kresistor.  
Valid  
Strobe  
Valid  
Strobe  
Invalid  
Strobe  
ST  
tST  
tRST  
The PBRST can be driven from a TTL or CMOS logic line or  
shorted to ground with a mechanical switch.  
tTD (min)  
tTD (max)  
RESET  
t
PB  
Note: ST is ignored whenever a reset is active  
PBRST  
Figure 5: Timing Diagram: Strobe Input  
V
IH  
t
PDLY  
Timeouts periods of approximately 150ms, 610ms or  
1,200ms are selected through the TD pin.  
V
IL  
t
RST  
Watchdog Time-out Period  
TD Voltage level  
(ms)  
RESET  
RESET  
VOH  
VOL  
Min  
Nom  
Max  
GND  
Floating  
VCC  
62.5  
250  
500  
150  
610  
250  
1000  
2000  
Figure 3: Timing Diagram: Pushbutton Reset  
1200  
Supply  
Voltage  
The watchdog timer can not be disabled. It must be strobed  
with a high-to-low transition to avoid watchdog timeout and  
reset.  
ASM1832  
1
2
8
7
V
CC  
PBRST  
T
D
I/O  
ST  
µP  
3
4
6
Supply  
Voltage  
TOL  
RESET  
5
GND RESET  
RESET  
ASM1832  
MREQ  
1
2
8
7
V
CC  
PBRST  
Figure 4: Application Circuit: Pushbutton Reset  
T
D
ST  
µP  
Decoder  
3
4
6
Watchdog Timer and ST Input  
TOL  
RESET  
RESET  
Address  
Bus  
RESET  
A watchdog timer stops and restarts a microprocessor that is  
“hung-up”. The µP must toggle the ST input within a set  
period (as selectable through TD input) to verify proper  
software execution. If the ST is not toggled low within the  
5
GND  
Figure 6: Application Circuit: Watchdog Timer  
3.3V µP Power Supply Monitor and Reset Circuit  
4 of 9  
Notice: The information in this document is subject to change without notice