October 2006
rev 1.6
ASM1832
Parameter
Symbol
tTD
Conditions
TD = VCC
Min
500
250
Typ
1200
610
Max
2000
1000
Unit
ms
Watchdog Timeout Period
Watchdog Timeout Period
tTD
TD Floating
ms
I=-500µA, VCC < 2.7.V Note
1
VOH
VCC - 0.3V
VCC - 0.1V
350
Output Voltage
V
IOH
IOL
IIL
Output = 2.4V, VCC >=2.7V
Output = 0.4V, VCC >=2.7V
Output Current
µA
mA
µA
V
Output Current
10
Input Leakage
-1.0
1.0
0.4
VOL
RESET Low Level
Internal Pull-up Resistor
Note 1
PBRST pin
40
kΩ
Outputs open, VCC <= 3.6V
and all inputs at VCC or GND
ICC1
Operating Current
20
µA
CIN
Input Capacitance
Output Capacitance
5
7
pF
pF
COUT
PBRST Manual Reset
Minimum Low Time
tPB
PBRST = VIL
20
ms
ms
tRST
Reset Active Time
250
610
1000
Must not exceed tRD mini-
tST
ST Pulse Width
20
20
ns
mum. Watchdog cannot be
disabled.
VCC Fail Detect to RESET or
Pulses < 2 µs at VCCTP min-
imum will not cause reset
tRPD
tF
5
8
µs
µs
RESET
VCC Slew Rate
PBRST Stable LOW to
RESET and RESET Active
tPDLY
20
ms
V
CC Detect to RESET or
tRPU
tR
trise=5µs
250
0
610
1000
ms
ns
RESET inactive
VCC Slew Rate
Notes
1. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC
falls below 2.0V.
3.3V µP Power Supply Monitor and Reset Circuit
6 of 9
Notice: The information in this document is subject to change without notice
PULSECORE [ PulseCore Semiconductor ]
