ASM1810
February 2005
rev 1.4
Application Information
Operation - Power Monitor
tR
The ASM1810 detects out-of-tolerance power supply
conditions. It resets a processor during power-up, power-down
and issues a reset to the system processor when the monitored
power supply voltage is below the reset threshold. When an
out-of-tolerance VCC voltage is detected, the RESET signal is
VCCTP (MAX)
VCCTP
VCCTP (MIN)
asserted. On power-up, RESET is kept active (LOW) for
approximately 150ms after the power supply voltage has
reached the selected tolerance. This allows the power supply
and microprocessor to stabilize before RESET is released.
t
RPU
VCC
V
OH
ASM1810
RESET
Figure 2: Timing Diagram: Power-Up
Microprocessor
RESET
RESET
100kΩ
Figure 1: RESET Valid to 0V V
CC
tF
VCC
VCCTP (MAX)
VCCTP
VCCTP (MIN)
Output Conditions
The ASM1810 active LOW reset signal is valid as long as VCC
remains above 1.2V. However the RESET output on the
ASM1810 uses a push-pull drive stage that can maintain a valid
output below 1.2V. To sink current with VCC below 1.2V, a
t
RESET
RPD
resistor can be connected from the reset pin (RESET) to
Ground (see Figure 1). This configuration will give a valid value
on the RESET output with VCC approaching 0V. During both
power up and down, this configuration will draw current when
the RESET is in the high state. A value of 100kΩ should be
adequate to maintain a valid connection.
V
OL
Figure 3: Timing Diagram: Power-Down
3 of 9
Low Power, 5V µP Reset
Notice: The information in this document is subject to change without notice
PULSECORE [ PulseCore Semiconductor ]
