November 2006
rev 1.6
ASM1232LP/LPS
Parameter
Symbol
IIL
Conditions
Min
Typ
Max
1.0
Unit
Input Leakage
Note 1
Note 3
Note 1
-1.0
µA
V
VOL
RESET Low Level
0.4
Internal Pull-up Resistor
Operating Current (CMOS)
Input Capacitance
40
kΩ
µA
pF
pF
ICC1
CIN
30
5
COUT
Output Capacitance
10
PBRST Manual Reset
Minimum Low Time
tPB
PBRST = VIL
Note 4
20
ms
tRST
tST
Reset Active Time
ST Pulse Width
250
20
610
5
1000
8
ms
ns
VCC Fail Detect to RESET or
RESET
tRPD
tF
µs
µs
VCC Slew Rate
4.75V to 4.25V
300
PBRST Stable LOW to RESET and
RESET Active
tPDLY
20
ms
V
CC Detect to RESET or RESET
tRPU
tR
tRISE = 5µs
250
0
610
1000
ms
ns
inactive
VCC Slew Rate
4.25V to 4.75V
Notes
1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC
falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (tTD). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.
6 of 10
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
PULSECORE [ PulseCore Semiconductor ]
