October 2003
rev 1.0
P2040A
Block Diagram
DIV2
SSON#
VDD
SR0 SR1 MRA
Modulation
PLL
CLKIN
Frequency
Divider
Output
Divider
Phase
Detector
Loop
Filter
VCO
Feedback
Divider
ModOUT
VSS
Pin Configuration
1
8
7
6
5
CLKIN
VDD
SR0
2
3
4
MRA
P2040A
ModOUT
SSON#
SR1
VSS
Pin Description
Pin
Pin#
Type
Description
Name
1
2
CLKIN
MRA
I
I
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull-up
resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull-up
resistor.
3
4
SR1
VSS
I
P
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal
pull-low resistor.
5
SSON#
I
6
7
8
ModOUT
SR0
O
I
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up
resistor.
VDD
P
Power supply for the entire chip (3.3V)
LCD Panel EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
