LNK623-626
Clampless Designs
shown on the right of Figure ±± where pulse grouping has
caused an increase in the output ripple.
Clampless designs rely solely on the drain node capacitance to
limit the leakage inductance induced peak drain-to-source
voltage. Therefore the maximum AC input line voltage, the value
of VOR, the leakage inductance energy, (a function of leakage
inductance and peak primary current), and the primary winding
capacitance determine the peak drain voltage. With no signifi-
cant dissipative element present, as is the case with an external
clamp, the longer duration of the leakage inductance ringing can
increase EMI.
To eliminate group pulsing verify that the feedback signal settles
within 2.± μs from the turn off of the internal MOSFET. A Zener
diode in the clamp circuit may be needed to achieve the desired
settling time. If the settling time is satisfactory, then a RC
network across RLOWER (R6) of the feedback resistors is
necessary.
The value of R (R1 in the Figure ±2) should be an order of
magnitude greater than RLOWER and selected such that
R×C = 32 μs where C is C1 in Figure ±2.
The following requirements are recommended for a universal
input or 230 VAC only Clampless design:
±. Clampless designs should only be used for PO ≤1 W using a
Quick Design Checklist
V
OR of ≤90 V
2. For designs with PO ≤1 W, a two-layer primary must be used
to ensure adequate primary intra-winding capacitance in the
range of 21 pF to 10 pF. A bias winding must be added to
the transformer using a standard recovery rectifier diode
(±N4003– ±N4007) to act as a clamp. This bias winding may
also be used to externally power the device by connecting a
resistor from the bias winding capacitor to the BYPASS pin.
This inhibits the internal high-voltage current source,
reducing device dissipation and no-load consumption.
3. For designs with PO >1 W, Clampless designs are not practical
and an external RCD or Zener clamp should be used.
4. Ensure that worst-case, high line, peak drain voltage is below
the BVDSS specification of the internal MOSFET and ideally
≤610 V to allow margin for design variation.
As with any power supply design, all LinkSwitch-CV designs
should be verified on the bench to make sure that component
specifications are not exceeded under worst-case conditions.
5
D6
1N4148
4
R3
6.34 k7
1%
2
LinkSwitch-CV
U1
LNK626PG
D
S
FB
BP
V
OR (Reflected Output Voltage), is the secondary output plus
R5
R4
6.2 k7
output diode forward voltage drop that is reflected to the primary
via the turns ratio of the transformer during the diode conduction
time. The VOR adds to the DC bus voltage and the leakage spike
to determine the peak drain voltage.
47 k7
1/8 W
R6
C6
4.02 k7
10 MF
C4
C5
680 pF
50 V
1%
50 V
1 MF
50 V
Pulse Grouping
PI-5268-110608
Pulse grouping is defined as 6 or more consecutive pulses
followed by two or more timing state changes. The effect of
pulse grouping is increased output voltage ripple. This is
Figure 12. RC Network Across RBOTTOM (R6) to Reduce Pulse Grouping.
Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (10 mV/div)
Split Screen with Bottom Screen Zoom
Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (10 mV/div)
Figure 11. Not Pulse Grouping (<5 Consecutive Switching Cycles).
Pulse Grouping (>5 Consecutive Switching Cycles).
9
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Rev. E 09/09
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