LNK584-586
The LinkZero-AX device is self biased through the DRAIN pin.
An optional external bias, can be derived either from a third
winding or from an output voltage rail in non-isolated designs.
By providing an external supply current in excess of IS2 (310 mA
for the LNK584) the internal 5.85 V regulator circuit is disabled
providing a simple way to reduce device temperature and
improve efficiency, especially at high line.
may also be used as a preload too. Recommended value of the
feedback resistors is such that they should draw ~1% of full load
current. Finally a capacitor in parallel to the high side feedback
resistor can be used to increase the speed of the loop (C9 in
Figure 4).
These recommendations apply for full load to zero load transients.
For applications with more limited load range, the preload and
the capacitor in parallel to the high side feedback resistor may
not be necessary.
A clampless primary circuit is achieved due to the very tight
tolerance current limit device, plus the transformer construction
techniques used. The peak drain voltage is therefore limited to
typically less than 550 V at 265 VAC, providing significant margin
to the 700 V minimum drain voltage specification (BVDSS).
Layout Considerations
LinkZero-AX Layout Considerations
Output rectification and filtering is achieved with output rectifier
D6 and filter capacitor C6. Due to the auto-restart feature, the
average short-circuit output current is significantly less than 1 A,
allowing low current rating and low cost rectifier D6 to be used.
Output circuitry is designed to handle a continuous short-circuit
on the power supply output. In this design a preload resistor R13
is used at the output of the supply to prevent automatic
Layout
See Figure 5 for a recommended circuit board layout for
LinkZero-AX (U1).
Single Point Grounding
Use a single point ground (Kelvin) connection from the input
filter capacitor to the area of copper connected to the SOURCE
pins.
triggering of the Power-Down mode when the load is removed.
LinkZero-AX Power-Down (PD) Mode
Design Considerations
Bypass Capacitor (CBP), FEEDBACK Pin Noise Filter
Capacitor (CFB) and Feedback Resistors
To minimize loop area, these two capacitors should be physically
located as near as possible to the BYPASS and SOURCE pins,
and FEEDBACK pin and source pins respectively. Also note
that to minimize noise pickup, feedback resistors RFB1 and RFB2
are placed close to the FEEDBACK pin.
LinkZero-AX goes into Power-Down mode when 160 consecutive
switching cycles have been skipped. This condition occurs
when the output load is low or the FEEDBACK pin is pulled high
(for example through Q1 and R16 in Figure 4). The value of the
BYPASS pin capacitor must be high enough to sustain enough
current through R16 for more than the period of 160 switching
cycles to successfully trigger the Power-Down mode. At low line
input voltage (90 VAC) the 160 switching cycle period is ~1.6 ms
as the internal oscillator frequency is 100 kHz. However as the
input line voltage increases, the internal oscillator frequency is
gradually reduced to keep the maximum output power relatively
constant. At high line (265 VAC) therefore, the internal oscillator
frequency can be as low as 78 kHz (see parameter table Note C).
Therefore to provide sufficient margin to ensure Power-Down
mode is triggered it is recommended that the Power-Down pulse
(see Figure 1) is 2.5 ms (200 switching cycles at 80 kHz).
LinkZero-AX stops switching once the Power-Down mode is
triggered. The IC does not resume switching until the BYPASS
pin is pulled below 1.5 V using the reset/wake up pulse (see
Figure 1) and then allowed to recharge back up to 5.85 V
through the drain connected 5.85 V regulator block. Transistor
Q2 or mechanical switch SW1 can be used for resetting the
Power-Down mode either electronically or mechanically.
Primary Loop Area
The area of the primary loop that connects the input filter
capacitor, transformer primary and LinkZero-AX should be kept
as small as possible.
Primary Clamp Circuit
An external clamp may be used to limit peak voltage on the
DRAIN pin at turn off. This can be achieved by using an RCD
clamp or a Zener (~200 V) and diode clamp across the primary
winding. In all cases, to minimize EMI, care should be taken to
minimize the circuit path from the clamp components to the
transformer and LinkZero-AX (U1).
Thermal Considerations
The copper area underneath the LinkZero-AX (U1) acts not only
as a single point ground, but also as a heat sink. As it is
connected to the quiet source node, this area should be
maximized for good heat sinking of U1. The same applies to
the cathode of the output diode.
It is important to design the power supply to ensure that load
transients and other external events do not unintentionally
trigger Power-Down mode by causing 160 consecutive switching
cycles to be skipped. It is recommended that a preload resistor
is added to draw ~2% of the full load current (12 mA at 5 V in a
3 W power supply). Although this reduces full load efficiency
slightly, it has no influence on the power consumption during
Power-Down mode since the power supply output is fully
discharged under this condition. Low value feedback resistors
Y Capacitor
The placement of the Y-type capacitor (if used) should be
directly from the primary input filter capacitor positive terminal to
the common/return terminal of the transformer secondary.
Such a placement will route high magnitude common-mode
surge currents away from U1. Note: If an input π EMI filter is
used, the inductor in the π filter should be placed between the
negative terminals on the input filter capacitors.
5
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