LNK562-564
TOP VIEW
FB
BP
CBP
D
Input Filter
Capacitor
S
S
S
S
Tr a n s f o r m e r
HV DC
INPUT
+
-
+
DC
OUT
-
Maximize hatched copper
areas (
) for optimum
heatsinking
Output Filter
Capacitor
PI-4157-101305
Figure 6. Recommended Circuit Board Layout for LinkSwitch-LP using P Package (Assumes a HVDC Input Stage).
DRAIN pin at turn off. This can be achieved by using an RCD
clamp or a Zener (~200 V) and diode clamp across the primary
winding. In all cases, to minimize EMI, care should be taken
to minimize the circuit path from the clamp components to the
transformer and LinkSwitch-LP.
LinkSwitch-LP Layout Considerations
Layout
See Figure 6 for a recommended circuit board layout for
LinkSwitch-LP (P & G package).
Thermal Considerations
Single Point Grounding
The copper area underneath the LinkSwitch-LP acts not only as
a single point ground, but also as a heatsink. As it is connected
to the quiet source node, this area should be maximized for
good heat sinking of LinkSwitch-LP. The same applies to the
cathode of the output diode.
Use a single point ground connection from the input filter
capacitor to the area of copper connected to the SOURCE pins.
Bypass Capacitor (CBP)
TheBYPASSpincapacitorshouldbelocatedasnearaspossible
to the BYPASS and SOURCE pins.
Y-Capacitor
The placement of the Y-type cap should be directly from the
primary input filter capacitor positive terminal to the common/
return terminal of the transformer secondary. Such a placement
will route high magnitude common-mode surge currents away
from the LinkSwitch-LP device. Note: If an input pi (C, L, C)
EMIfilterisused, thentheinductorinthefiltershouldbeplaced
between the negative terminals on the input filter capacitors.
Primary Loop Area
The area of the primary loop that connects the input filter
capacitor, transformer primary and LinkSwitch-LP together
should be kept as small as possible.
Primary Clamp Circuit
An external clamp may be used to limit peak voltage on the
6
Rev. H 11/08
POWERINT [ Power Integrations ]
