LNK500
Toaidthedesigner,thepowertablereflectsthesedifferences.For
CV/CC designs the typical power column and for CV designs
the minimum power column should be used, respectively.
Additionally, figures are based on the following conditions:
As primary inductance tolerance is part of the expression
that determines the peak output power point (start of the CC
characteristic) this parameter should be well controlled. For
an estimated overall constant current tolerance of ±25% the
primary inductance tolerance should be ±10% or better. This
is achievable using standard low cost, center leg gapping
techniques where the gap size is typically 0.08 mm or larger.
Smaller gap sizes are possible but require non-standard, tighter
ferrite AL tolerances.
1. The minimum DC input bus voltage is 90 V or higher. This
correspondstoafiltercapacitorof3µF/Wforuniversalinput
and 1 µF/W for 230 VAC or 115 VAC input with doubler
input stage.
2. Design is a discontinuous mode flyback converter.
Continuous mode designs can result in loop instability and
are therefore not recommended. For typical output power
figures, nominal values for primary inductance and I2f are
assumed. For minimum output power figures, primary
inductance minus 10% and the minimum I2f value are
assumed. For no-load consumption <300 mW, a VOR in the
range 40 V to 60 V is assumed. For no-load consumption
<500 mW and higher output power capability, a VOR in the
range 60 V to 100 V is assumed.
Other gapping techniques such as film gapping allow tighter
tolerances (±7% or better) with associated improvements in
the tolerance of the peak power point. Please consult your
transformer vendor for guidance.
Core gaps should be uniform. Uneven core gapping, especially
with small gap sizes, may cause variation in the primary
inductance with flux density (partial saturation) and make the
constant current region non-linear. To verify uniform gapping
it is recommended that the primary current wave-shape be
examined while feeding the supply from a DC source. The
gradient is defined as di/dt = V/L and should remain constant
throughout the MOSFET on time. Any change in gradient of
the current ramp is an indication of uneven gapping.
3. A secondary output of 5 V with a Schottky rectifier diode.
4. Assumed efficiency of 70%.
5. The part is board mounted with SOURCE pins soldered to
sufficient area of copper to keep the die temperature at or
below 100 °C.
6. An output cable with a total resistance of 0.2 Ω.
Measurements made using an LCR bridge should not be solely
reliedupon;typicallytheseinstrumentsonlymeasureatcurrents
of a few milliamps. This is insufficient to generate high enough
flux densities in the core to show uneven gapping.
In addition to the thermal environment (sealed enclosure,
ventilated, open frame, etc), the maximum power capability
of LinkSwitch in a given application depends on transformer
core size, efficiency, primary inductance tolerance, minimum
specifiedinputvoltage,inputstoragecapacitance,outputvoltage,
output diode forward drop, etc., and can be different from the
values shown in Table 1.
For a typical EE13 core using center leg gapping, a 0.08 mm
gap (ALG of 190 nH/t2) allows a primary inductance tolerance of
±10% to be maintained in standard high volume production.
This allows the EE13 to be used in designs up to 2.75 W with
less than 300 mWno-load consumption. If film gapping is used
then this increases to 3 W. Moving to a larger core, EE16 for
example, allows a 3 W output with center leg gapping.
Transformer Design
To provide an approximately CV/CC output, the transformer
should be designed to be discontinuous; all the energy stored
in the transformer is transferred to the secondary during the
MOSFET off time. Energy transfer in discontinuous mode is
independent of line voltage.
The transformer turns ratio should be selected to give a VOR
(output voltage reflected through secondary to primary turns
ratio) of 40 V to 60 V. In designs not required to meet 300 mW
no-load consumption targets, the transformer can be designed
with higher VOR as long as discontinuous mode operation is
maintained. This increases the output power capability. For
example, a 230 VAC input design using an EE19 transformer
corewithVOR >70V, iscapableofdeliveringupto5.5Wtypical
output power. Note: the linearity of the CC region of the power
supply output characteristic is influenced by VOR. If this is an
important aspect of the application, the output characteristic
should be checked before finalizing the design.
Thepeakpowerpointpriortoenteringconstantcurrentoperation
isdefinedbythemaximumpowertransferredbythetransformer.
The power transferred is given by the expression P= 0.5·LP·I2·f,
whereLPistheprimaryinductance,I2 istheprimarypeakcurrent
squared and f is the switching frequency.
To simplify analysis, the data sheet parameter table specifies an
I2f coefficient. This is the product of current limit squared and
switchingfrequencynormalizedtothefeedbackparameterIDCT
.
This provides a single term that specifies the variation of the
peak power point in the power supply due to LinkSwitch.
Output Characteristic Variation
Boththedevicetoleranceandexternalcircuitgoverntheoverall
tolerance of the LinkSwitch output characteristic. Estimated
peak power point tolerances for a 3 W design are ±10% for
D
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2/05
POWERINT [ Power Integrations ]
