LNK454/456-458/460
Bleeder Circuit
limits the maximum capacitance on the DC side of the input
bridge rectifier. Typically the maximum capacitance value
needed for high power factor also results in meeting the 19 V
limit however during development, this should be verified on an
oscilloscope.
Resistor R10, R11 and C6 form a bleeder network which
ensures the initial input current is high enough meet the TRIAC
holding current requirement, especially during small conduction
angles. For non-dimming application R10, R11 and C6 may be
omitted.
If a reduction in capacitance is required and this results in
increased conducted EMI then capacitance may be added
before the input rectifier which effectively isolates it from the bus
capacitance.
Input Rectifier and EMI Filter
EMI filtering is provided by L1 and a pi (π) filter formed by C4, L2
and C5. Resistors R2 and R9 dampen the self resonances of
the filter stages and reduce the resultant peaks in the
conducted EMI spectrum. As shown the design meets
EN55015 conducted limits with >20 dB margin.
For applications intended for use with leading edge TRIAC
dimmers, film capacitors are recommended as ceramic
capacitors typically create audible noise.
The incoming AC is rectified by BR1 and filtered by C4 and C5.
The total effective input capacitance, the sum of C4 and C5,
was selected to ensure correct zero crossing detection of the
AC input by the LinkSwitch-PL device, necessary for correct
dimming operation.
Output Capacitor Selection
Output capacitance has a direct effect on the output load (LED)
ripple current. The larger the capacitance, the lower the ripple
current. Excessive capacitance can prevent the output reaching
regulation within the auto-restart time and either cause failure to
start or require several start-up attempts (hiccups). Too little
capacitance can cause the voltage of the FEEDBACK pin to
exceed the cycle skipping mode threshold, degrading PF and
causing output flicker while dimming.
Primary Components
The LNK457DG device (U1) incorporates the power switching
device, oscillator, CC control engine, startup, and protection
functions. The integrated 725 V power MOSFET provides
extended design margin, improving robustness during line
surge events even in high line applications. The device is
powered from the BYPASS pin via the decoupling capacitor C9.
At start-up, C9 is charged by U1 from an internal current source
via the DRAIN pin and then during normal operation it is
supplied by the output via R15 and D4. For non-dimming
designs D4 and R15 may be omitted.
Therefore the output capacitance value should be selected
such that the ripple voltage across the output current sense
resistor (R18 in Figure 7) and fed into the FEEDBACK pin is
within the range of 100 mVp-p ≤ VFEEDBACK ≤ 400 mVp-p with a
target value of 290 mVp-p.
The output capacitor type is not critical. Non-electrolytic
capacitors are attractive in terms of lifetime (ceramics and solid
dielectric types do not have an electrolyte that evaporates over
time) however electrolytic types offer the best volumetric
efficiency vs. cost. If multi-layer ceramics are selected, verify
the data sheet curves of capacitance vs. applied voltage and
temperature coefficient. The typical capacitance value may be
50% lower across temperature and/or close to rated voltage.
For all capacitor types verify the capacitor(s) selected are rated
for the output ripple current. For electrolytic types, this requires
selecting a low ESR type. A temperature rating of 105 °C or
higher is recommended for long lifetime. For typical designs
there is minimal self heating of the output capacitor and
therefore lifetime is determined by the internal ambient
temperature and broadly follows the Arrhenius equation, i.e.
lifetime doubles for every 10 °C drop in operating temperature.
For example the selection of a capacitor with a rated life of
5,000 hours at 105 °C would have an expected lifetime of
40,000 hours at 75 °C. End of life is typically defined for an
electrolytic capacitor as a doubling of the ESR and the
capacitance reducing by 20%. This often has little impact to
the performance seen by the end user and extends the fit for
purpose lifetime.
The rectified and filtered input voltage is applied to one end of
the primary winding of T1. The other side of the transformer’s
primary winding is driven by the integrated power MOSFET in
U1. The leakage inductance drain voltage spike is limited by an
RCD-R clamp consisting of D2, R13, R12, and C7.
Diode D6 is used to protect the IC from negative ringing (drain
voltage below source voltage) when the power MOSFET is off
and the input voltage is below the reflected output voltage (VOR).
Output Rectification
The secondary of the transformer is rectified by D5, a Schottky
barrier type for higher efficiency, and filtered by C11. Resistor
R17 and C10 damp high frequency ringing and improve
conducted and radiated EMI.
Output Feedback
The CC mode set-point is determined by the voltage drop that
appears across R18 which is then fed to the FEEDBACK pin of
U1. Output overvoltage protection is provided by VR2 and R21.
Application Considerations
Input Capacitor Selection
Feedback Pin Signal
During normal non-dimming (full power) operation, the FEEDBACK
pin threshold voltage (the voltage developed across the current
sense resistor) is 290 mV. For best output current regulation,
between 100 mVp-p to 400 mVp-p of voltage ripple is recommended.
For correct operation during dimming, the LinkSwitch-PL device
must detect line voltage zero crossing. This is sensed internally
via the drain node at the point the DC bus falls to <19 V. The
requirement for the DC bus to reach this level on each half-cycle
7
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Rev. A 11/01/10
POWERINT [ Power Integrations ]
