InnoSwitch-CH
Pin Functional Description
InnoSwitch-CH Functional Description
DRAIN (D) Pin (Pin 1)
This pin is the power MOSFET drain connection.
The InnoSwitch-CH combines a high-voltage power MOSFET switch
and both primary-side and secondary-side controllers in one device.
The feedback scheme using a proprietary FluxLink coupling scheme
using the package lead frame and bond wires to provide a reliable
and low-cost means to provide accurate direct sensing of the output
voltage and output current on the secondary to communicate
information to the primary IC. Unlike conventional PWM (pulse width
modulated) controllers, it uses a simple ON/OFF control to regulate
the output voltage and current. The primary controller consists of an
oscillator, a receiver circuit magnetically coupled to the secondary
controller, current limit state machine, 5.95 V regulator on the
PRIMARY BYPASS pin, overvoltage circuit, current limit selection
circuitry, over temperature protection, leading edge blanking and a
650 V power MOSFET. The InnoSwitch-CH secondary controller
consists of a transmitter circuit that is magnetically coupled to the
primary receiver, constant voltage (CV) and constant current (CC)
control circuitry, a 4.45 V regulator on the SECONDARY BYPASS pin,
synchronous rectifier MOSFET driver, frequency jitter oscillator and a
host of integrated protection features. Figures 3 and 4 show the
functional block diagrams of the primary and secondary controllers
with the most important features.
SOURCE (S) Pin (Pin 3-6)
This pin is the power MOSFET source connection. It is also the
ground reference for the PRIMARY BYPASS pin.
PRIMARY BYPASS (BPP) Pin (Pin 7)
It is the connection point for an external bypass capacitor for the
primary IC supply.
NO CONNECTION (NC) Pin (Pin 8)
This pin should be left open or tied to PRIMARY BYPASS pin.
NO CONNECTION (NC) Pin (Pin 9)
This pin should be left open.
FORWARD (FWD) Pin (Pin 10)
The connection point to the switching node of the transformer output
winding for sensing and other functions.
OUTPUT VOLTAGE (VOUT) Pin (Pin 11)
This pin is connected directly to the output voltage of the power
supply to provide bias to the secondary IC.
PRIMARY BYPASS Pin Regulator
SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 12)
The PRIMARY BYPASS pin has an internal regulator that charges the
PRIMARY BYPASS pin capacitor to VBPP by drawing current from the
voltage on the DRAIN pin whenever the power MOSFET is off. The
PRIMARY BYPASS pin is the internal supply voltage node. When the
power MOSFET is on, the device operates from the energy stored in
the PRIMARY BYPASS pin capacitor. Extremely low power consump-
tion of the internal circuitry allows the InnoSwitch-CH to operate
continuously from current it takes from the DRAIN pin.
Connection to external SR FET gate terminal.
SECONDARY BYPASS (BPS) Pin (Pin 13)
It is the connection point for an external bypass capacitor for the
secondary IC supply.
FEEDBACK (FB) Pin (Pin 14)
This pin connects to an external resistor divider to set the power
supply CV voltage regulation threshold.
In addition, there is a shunt regulator clamping the PRIMARY BYPASS
pin voltage to VSHUNT when current is provided to the PRIMARY
BYPASS pin through an external resistor. This facilitates powering the
InnoSwitch-CH externally through a bias winding to decrease the
no-load consumption to less than 10 mW (5 V output design).
SECONDARY GROUND (GND) (Pin 15)
Ground connection for the secondary IC.
ISENSE (IS) Pin (Pin 16)
Connection to the power supply output terminals. Internal current
sense is connected between this pin and the SECONDARY GROUND pin.
PRIMARY BYPASS Pin Capacitor Selection
The PRIMARY BYPASS pin can use a ceramic capacitor as small as
0.1 mF for decoupling the internal power supply of the device. A
larger capacitor size can be used to adjust the current limit. A 1 mF
capacitor on the PRIMARY BYPASS pin will select a higher current limit
equal to the standard current of the next larger device. A 10 mF
capacitor on the PRIMARY BYPASS pin selects a lower current limit
equal to the standard current limit of the next smaller device
ꢆ ꢂ
ꢂꢓ IS
PRIMARY BYPASS Pin Undervoltage Threshold
The PRIMARY BYPASS pin undervoltage circuitry disables the power
MOSFET when the PRIMARY BYPASS pin voltage drops below VBPP-VBPP(H)
in steady-state operation. Once the PRIMARY BYPASS pin voltage
falls below this threshold, it must rise back above VBPP to enable
switching the power MOSFET.
ꢂꢑ ꢒꢁꢆ
ꢂꢐ ꢄꢎ
ꢂꢍ ꢎꢏS
ꢂꢋ Sꢌ
ꢂꢂ ꢇꢈꢉꢊ
ꢂꢃ ꢄꢅꢆ
ꢀ ꢁC
S ꢍ-ꢓ
ꢎꢏꢏ ꢔ
ꢁC ꢕ
PRIMARY BYPASS Pin Output Overvoltage Latching Function
The PRIMARY BYPASS pin has an OV protection latching feature.
A Zener diode in parallel to the resistor in series with the PRIMARY
BYPASS pin capacitor is typically used to detect an overvoltage on the
primary bias winding to activate this protection mechanism. In the
event the current into the PRIMARY BYPASS pin exceeds (ISD) the
device will disable the power MOSFET switching. The latching
condition is reset by bringing the primary bypass below the reset
threshold voltage (VBPP(RESET)).
ꢀꢁꢂ7ꢃꢄꢅꢂ07ꢆꢄ1ꢇ
Figure 5. Pin Configuration.
3
Rev. J 10/17
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