DI-22
Toreducewindinganddiodedissipationthesecondaryissplit
into two windings and diode OR’ed into the output capacitors
(C2, 3). Regulation is provided by a secondary side reference
(U3), the output voltage sensed by R4, R13 and R6.
TRANSFORMER PARAMETERS
FPQ26/20-A
Core Material
TDK PC40 gappped for ALG = 843 nH/T2
Bobbin
TDK BPQ26/20-1112CP
Key Design Points
Primary: 9T + 9T, 2 x 26 AWG
Shield: 1T, 8 mm x 0.015 mm Cu foil
Secondary 1: 3T, 3 x 26 AWG T.I.W.
Secondary 2: 3T, 3 x 26 AWG T.I.W.
Bias: 2T, 8 mm x 0.015 mm Cu foil
(T.I.W. = Triple Insulated Wire)
• D1 and VR1 clamp leakage inductance spikes. A Zener
clamp provides lower zero load consumption than an RCD
clamp and higher efficiency below full load.
• C11 reduces VR1 dissipation, raising efficiency.
• AdditionaldifferentialfilteringisprovidedbyC13andL3.
• C12 provides high frequency bypass, reducing high
frequency EMI.
Winding Details
Primary (2-1), Shield (1-NC),
tape, Secondary 1 (12-9),
Secondary 2 (11-8),
Bias (6-5), tape, Primary (3-2), tape
Winding Order
(Pin Numbers)
• Use foil windings to reduce dissipation and reduce leakage
inductance.
Primary: 273 µH ± 10%,
Leakge: 3 µH (maximum)
Inductance
• Sandwich secondary winding between two halves of
primary to reduce leakage inductance.
Primary Resonant
Frequency
1.5 MHz (minimum)
• High core temperature reduces saturation flux density.
Keep flux density below 3000 gauss (0.3 T) to prevent
saturation.
Table 1. Transformer Construction Information.
• Use 100 V Schottky diodes for highest efficiency.
• Good layout practices should be followed:
- Locate C8, R3, C5, R9, R10 and R11 close to U1.
- Power and signal source currents should be separated,
joined using a Kelvin connection at the SOURCE pin.
- Minimizetheprimaryandsecondaryloopareastoreduce
parasitic leakage and EMI.
• Consult DAK-11 and EPR-11 for more information.
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Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any
license under its patent rights or the rights of others.
The products and applications illustrated herein may be covered by one or more U.S. and foreign patents or potentially by pending U.S.
and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at
www.powerint.com.
The PI Logo, TOP S w it c h , Tin yS w it c h and Ec o S m a rt are registered trademarks of Power Integrations, Inc.
P I Ex p e rt is a trademark of Power Integrations, Inc. ©Copyright 2002, Power Integrations, Inc.
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