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CAP006DG-TL 参数 Datasheet PDF下载

CAP006DG-TL图片预览
型号: CAP006DG-TL
PDF下载: 下载PDF文件 查看货源
内容描述: [IC CAPACITOR DISCHARGE 8SO]
分类和应用:
文件页数/大小: 8 页 / 782 K
品牌: POWERINT [ Power Integrations ]
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CAPZero  
For MOV placement that is not directly across the X Capacitor1 (for  
example MOVPOS2 in Figure 3) the 1000 V CAPZero devices can be  
used up to a surge specification of 1.5 kV. For differential surge  
voltage specifications of >1.5 kV it is recommended that the MOV is  
Pin Functional Description  
The pin configuration of Figure 2 ensures that the width of the SO-8  
package is used to provide creepage and clearance distance of over  
4 mm.  
always placed in the location shown in Figure 3 as MOVPOS1  
.
Although electrical connections are only made to pins 2, 3, 6 and 7, it  
is recommended that pins 1-4 and pins 5-8 are coupled together on  
the PCB – see Applications Section.  
It is always recommended that the peak voltage between terminals  
D1 and D2 of CAPZero is measured during surge tests in the final  
system. Measurements of peak voltage across CAPZero during surge  
tests should be made with oscilloscope probes having appropriate  
voltage rating and using an isolated supply to the oscilloscope to  
avoid ground currents influencing measurement results. When  
making such measurements, it is recommended that 50 V engineer-  
ing margin is allowed below the breakdown voltage specification (for  
example 950 V with the 1000 V CAPZero).  
D Package (SO-8)  
8
7
6
5
1
2
NC  
D1  
NC  
D2  
If the measured peak Drain voltage exceeds 950 V, an external 1 kV  
ceramic capacitor can be placed between D1 and D2 terminals to  
attenuate the voltage applied between the CAPZero terminals during  
surge. Please refer to the Application Note AN-48 for the details.  
This optional external capacitor placement is shown as CEXT in Figure  
3. It should be noted that use of an external capacitor in this way will  
increase power consumption slightly due to the CEXT charge/discharge  
currents flowing in R1 and R2 while AC is connected.  
3
4
D2  
D1  
NC  
NC  
PI-5608-060810  
PCB Layout and External Resistor Selection  
Figure 4 shows a typical PCB layout configuration for CAPZero. The  
external resistors in this case are divided into two separate surface  
mount resistors to distribute loss under fault conditions – for example  
where a short-circuit exists between CAPZero terminals D1 and D2.  
R1 and R2 values are selected according to Table 1.  
Figure 2. Pin Configuration.  
Key Application Considerations  
Breakdown Voltage Selection  
Figure 3 illustrates possible system configurations influencing the  
choice of CAPZero breakdown voltage. The system configuration  
variables include the placement of the system MOV and X capacitor(s)  
as well as the differential surge voltage specifications of the  
application.  
Under a fault condition where CAPZero terminals D1 and D2 are  
shorted together, each resistor will dissipate a power that can be  
calculated from the applied AC voltage and the R1 and R2 values. For  
example in an application using CAP004 or CAP014, R1=R2=390 kW.  
If CAPZero is shorted out at 265 VAC R1 and R2 will each dissipate  
45 mW.  
As shown in Table 1, each device in the CAPZero family has a 825 V  
or 1000 V option. For applications where the system MOV is placed  
in position 1 (MOVPOS1 in Figure 3), the 825 V option will typically  
provide adequate voltage withstand for surge requirements up to 3 kV  
or more. The 1 kV CAPZero would be recommended for higher surge  
requirements or if additional voltage margin is required.  
Resistors R1 and R2 should also be rated for 50% of the system input  
voltage again to allow for the short-circuitry of CAPZero D1 to D2 pins  
during single point fault testing.  
R1  
D1  
MOVPOS1  
MOVPOS2  
Other EMI  
Filter  
Components  
CEXT  
AC  
X Capacitor1  
X Capacitor2  
D2  
CAPZero  
R2  
PI-6600-110711  
Figure 3. Placement Options of MOV and CEXT  
.
2
Rev. H 03/18  
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