PS0020
Light Load Operation
Enable Input
The PS0020 provides improved light load efficiency.
The internal zero current comparator monitors the
inductor current to the load and shuts off the PMOS
switch once this current reduces to some low value
(50mA, typically). This prevents the inductor
current from reversing its polarity, avoiding back-
charging and thus improving efficiency at light load.
At that time, both the NMOS and PMOS switches
remain off. However, normal operation starts again
when the output voltage falls below the regulation
point. The IC automatically skips pulses at light
load, providing better efficiency.
The PS0020 features an active-high CMOS input
enable pin (SHUTB) that allows on/off control of the
regulator. When SHUTB=Low, shutdown of the chip
occurs and at that time almost no quiescent current
(<1μA) flows. Output capacitor can be completely
discharged through the load or the feedback
resistors for real output shut down. A discharge
switch is internally connected between Vin and SW.
The Enable (SHUTB) input threshold is TTL/CMOS
compatible. Connect SHUTB to Vin for normal
operation.
Track Mode
Anti-ringing Control
The PS0020 is in track mode when Vin is greater
than the output voltage regulation point (in
abnormal boost converter operation). In track
mode, the regulator runs at fixed start-up oscillator
frequency. The start-up oscillator runs freely until
Vout exceeds Vin. When Vout falls below Vin, the
start-up oscillator is enabled again. Thus in track
mode, normal loop control of PWM operation
remains off, rather the regulator runs by
intermittent oscillator operation.
When inductor current goes to zero, there arises a
high frequency ringing of SW pin. To prevent this
phenomenon, a 100Ω discharge switch is provided
between SW and VIN, so that this high frequency
ringing is damped out.
Under Voltage Lockout
When the supply goes too low (below 1.8V typ),
the PS0020 produces an internal UVLO (under
voltage lockout) signal that disables the normal
PWM operation and enables the start-up oscillator
to run at a fixed frequency. At that time, very few
circuits are operational. When the oscillator raises
the supply above 1.9V, UVLO signal is disabled and
the normal PWM mode takes over the start-up
oscillator operation. This mechanism protects the
chip from producing false logic due to low input
supply.
Version 1.1
July 6, 2007
www.picsemi.com
© 2007 Power IC. All Rights Reserved.
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