Ana lo g Line Sc a n Ca m e ra
Figure 3: Master Mode Timing Diagram
CCLK
16 Clock Cycles
CLT
12 Clock Cycles
N Clock Cycles
12 Cycles
LEN
1 Clock Cycle
1 Clock Cycle
Analog
Video
10 Dark pixels
...
1
2
N-1
N
Note: N is the number of active pixels on the sensor
Figure 4: Slave Mode Timing Diagram
2 Clock
Cycles
min.
2 Clock Cycles min.
LT
2 Clock Cycles +
Exposure period
1.2usec min.
LR
4 Clock
Cycles
min.
Line period
4 Clock Cycles min.
CCLK
MCLK
1 Clock Cycle
16 Clock Cycles
CLT
12 Clock
Cycles min.
N Clock Cycles
LEN
12 Clock
Cycles min.
1 Clock Cycle 1 Clock Cycle
10 Dark
pixels
Analog
Video
...
N-1
N
1
2
Note 1: N = number of active pixels on the sensor
Note 2: E = extra pixel
w w w . p e r k in e lm e r . c o m / o p t o
DSP-201.01D - 4/2002 Page 4
PERKINELMER [ PERKINELMER OPTOELECTRONICS ]
