Ana lo g Line Sc a n Ca m e ra
Figure 2: LC3000 Camera Block Diagram
Camera Mode Select
RS-422 Receivers
+LT
FPGA
2
Dip Switch
Position 1 and 2
CAMERA
TIMING
LOGIC
LINE
TRANSFER
LOGIC
ØH1
ØH2
-LT
D
R
I
V
E
+MCLK
-MCLK
+LRn
-LRn
CLK
LOGIC
ØTG
ØPG
ØRG
ØAB
I
L
E
V
E
L
T
R
A
N
S
L
O
G
I
M
A
G
E
Exposure
Control
Logic
C
R
RS-422 Drivers
+CCLK
-CCLK
Line Enable Logic
VSP TIMING LOGIC
LENS
+CLT
-CLT
Gain Range Select
Dip Switch
Position 3-5
+LEN
-LEN
VIDEO SIGNAL
PROCESSING
3
3
Dip Switch
Position 6-8
+V
out
OFFSET
CONTROL
GAIN
CONTROL
C
D
S
Offset Range Select
Amp
-V
out
Single
D.C
Power
Supply
Input
12-24V
DIP-switches. These switches are
accessible behind a removable panel,
located above the 25-pin connector on
the back plate of the camera. Figure 3
illustrates the timing details in Master
Mode.
to define the output video data rate,
as well as a properly timed Line
Transfer (LT) signal to initiate the line
readout. Figure 4 illustrates timing
details in slave mode. Table 1 details
correct DIP-switch settings for both
Master and Slave Mode.
with Line Reset (LR) and LT signals,
but allows the camera to run at the
maximum data rate determined by the
internal oscillator. Alternative Slave
Mode 2 instructs the camera to ignore
LR signals, which allows users to
bypass the exposure control feature
of the camera. Table 1 details all DIP-
switch settings for all operating
modes.
Slave Mode is to be selected when the
camera’s operations are to be synchro-
nized with the user’s unique system.
In slave mode, the camera requires an
external Master Clock signal (MLCK)
Within slave mode, there are two
alternative settings for unique appli-
cations. Alternative Slave Mode 1
allows the user to supply the camera
w w w . p e r k in e lm e r . c o m / o p t o
DSP-201.01D - 4/2002 Page 3
PERKINELMER [ PERKINELMER OPTOELECTRONICS ]
