Analog Line Scan Cameras
The Sensor
Figure 1a. Spectral Sensitivity Curve (1X Gain)
LC1917-series cameras contain a
high-performance, high-resolution line
scan image sensor (PerkinElmer
Optoelectronics parts RL1024PAG)
featuring a pinned photodiode pixel.
Each photodiode converts incident
light into discrete charge packets.
Advantages of pinned photodiode
pixels include linear exposure control,
the elimination of image lag, and the
reduction of photo response non-
uniformity (PRNU). For more specific
sensor specifications and information,
please consult the appropriate sensor
datasheet, available by contacting
PerkinElmer. Figure 1a details the
spectral sensitivity of the sensor,
while Figure 1b details the sensor’s
glass window light transmission curve.
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Right Scale
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Left Scale
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Wavelength (nm)
Functional Description
Figure 1b. Sensor Window Transmission Curve
The video signal from the sensor is
processed through a single channel of
sampled-and-held, raster order, analog
video data. The video channel signal
processing circuitry offers both
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0
adjustable gain and dark offset levels
to allow customization of the camera
to unique lighting applications. An
operational amplifier in a differential
configuration is recommended to
receive the video signal. Figure 2
details the camera video processing.
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Input Signals
Wavelength (nm)
The LC1917 camera requires DC supply
voltages of +12 VDC, -12 VDC, and
+5 VDC for operation. Table 3 further
describes power requirements and
voltages, along with tolerances. By
default, the camera will operate at its
maximum line rate of 4700 scans per
second. The camera is controlled by
two externally generated differential
input signals: Master Clock (MCLK)
and Line Transfer (LT).
Figure 2. Camera Block Diagram
CLT+
CLT-
LT+
LT-
Line Transfer Logic
LT
øH1
øH2
MCLK+
MCLK-
The Master Clock input determines
the data rate frequency for values up to
maximum clock of the camera (5 MHz).
The data rate may be run from 1 MHz
to cameras maximum clock rate.
øAB
øPG
MCLK
Logic
Drive
Logic
IMAGER
LENS
øRG
øTG
CCLK+
CCLK-
FPGA
The LT input signal transfers the
charge from each photosite to the
readout registers. The readout
LEN
Line Enable Logic
LEN+
LEN-
registers, in turn, transport the charge
from each photodiode in succession to
the video outputs. The LT input from
the user must remain in the ON state
for at least one and a half MCLK
cycles to initiate the internal line
transfer and may remain ON until one
VOUT
+
VIDEO
Amp
VOUT
-
Sample -
and - Hold
Offset
ADJ
Gain
ADJ
+12VDC
+5VDC
-12VDC
www.perkinelmer.com/opto
DSP-205.01A - 4/2001W Page 2
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