PSL12-N thru PSL14-N
SILICON EPITAXIAL PLANER TYPE
Low VF Chip Schottky Diodes
SOD-323
0.106 (2.7)
0.091 (2.3)
0.012(0.3) Typ .
0.057 (1.45)
0.041 (1.05)
0.047 (1.2)
0.031 (0.8)
0.016(0.4) Typ .
0.016(0.4) Typ .
Dimensions in inches and (millimeters)
FEATURES
Plastic package has Underwriters Laboratory
Flammability Classification 94V-0 Ufizing Flame
Retardant Epoxy Molding Compound.
For surface mounted applications.
Exceeds environmental standards of ML-S-19500/228
Low leakage current
MECHANICAL DATA
Case JEDEC SOD-323 molded plastic
Terminals Solder plated, solderable per
MIL-STD-750, Method 2026
Polarity Indicated by cathode band
Mounting Position Any
MAXIMUM RATINGS
(at T
A
=25 C unless otherwise noted)
o
PARAMETER
Forward rectified current
Forward surge current
See Fig.2
CONDITIONS
SYMBOL
I
O
I
FSM
Min.
Typ.
Max.
UNITS
A
A
mA
mA
0
1.0
30
1.0
10
80
130
-55
*4
8.3ms Single Half Sine-Wave Superimposed
on Rated Load (JEDEC Method)
V
R
=V
RRM
T
A
=25
0
C
V
R
=V
RRM
T
A
=100
0
C
Junction to ambient
F=1MHz and applied 4vDC reverse voltage
Reverse current
Thermal resistance
Diode junction capacitance
Storage temperature
I
R
R
JA
C
J
T
STG
*1
*2
*3
C/W
pF
+150
0
C
SYMBOLS
PSL12-N
PSL13-N
PSL14-N
MARKING CODE
L2
L3
L4
V
RRM
(V)
20
30
40
V
RMS
(V)
V
R
(V)
20
30
40
V
F
(V)
Operating Temperature
(
0
C)
14
21
28
0.38
0.40
0.40
-55 to + 125
*1 Repetitive peak reverse peak reverse
*2 RMS voltage
*3 Continuous reverse voltage
*4 Maximum forward voltage
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