UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions
Pin
Symbol*
Type
Description
1
2
3
4
5
6
7
8
9
A20MN
AD2
Output/Open Drain Legacy Gate A20 Output (Active-Low).
Bidir
Bidir
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Device Ground.
USB Clock (48 MHz).
Device Power (3.3 V).
AD1
AD0
VSS
CLK48
VDD
PMEN
PRTPWR1
Bidir
Power
Input
Power
Output/Open Drain Power Management Event (Active-Low).
Bidir
Input
Input
Port 1 Power. Logic output expected to turn on port 1 power. Boot-
strap low for high active. Bootstrap high for low active.
10
11
PWRFLT1N
PWROK1
Port 1 Power Fault (Active-Low). Logic input indicates an overcur-
rent fault on port 1.
Port 1 Power OK. Analog or digital input to inform the UHP112 that
USB port 1 power is stable (when >4 V).
12
13
14
15
16
17
18
19
20
21
VDDT
DPLS1
DMNS1
PMIENABLE
VSST
Power
Bidir
Bidir
Transceiver Power (3.3 V).
DIfferential USB Port 1 Signals.
Input
Power
Power
Bidir
Power Management Interface Enable Input (Active-High).
Transceiver Ground.
VDDT
Transceiver Power (3.3 V).
DPLS2
DMNS2
VSS
Differential USB Port 2 Signals.
Bidir
Power
Input
Device Ground.
TEST0
Test 0. For device testing. Connect this to ground during normal use.
Connect to logic high for NAND tree mode. See NAND Tree Mode
on page 2-32.
22
23
24
25
PWROK2
PWRFLT2N
PRTPWR2
TEST1
Input
Input
Bidir
Input
Port 2 Power OK. Analog or digital input to inform the UHP112 that
USB port 2 power is stable (when >4 V).
Port 2 Power Fault (Active-Low). Logic input indicates an overcur-
rent fault on port 2.
Port 2 Power. Logic output expected to turn on port 2 power. Boot-
strap low for high active. Bootstrap high for low active.
Test 1. For device testing. Tie this to ground during normal use.
Connect to logic high for NAND tree mode. See the NAND Tree
Mode section on page 2-32.
26
VDD5
Power
5 V Power for 5 V PCI Operation. 5 V must be present on this pin
while selecting either 3 V PCI or 5 V PCI operation with the VIO pin.
See PCI Connection Instructions section on page 2-26.
27
28
29
30
31
32
IRQ1
IRQ12
SMIN
INTAN
RSTN
CLK
Output/Open Drain System Keyboard Interrupt (Active-High).
Output/Open Drain System Mouse Interrupt (Active-High).
Output/Open Drain System Management Interrupt (Active-Low).
Output/Open Drain PCI Interrupt (Active-Low).
Input
Input
PCI Reset (Active-Low). Also the chip reset.
PCI Clock. 33 MHz input clock.
* Active-low signals within this document are indicated by an N following the symbol names.
Transdimension Inc.
5
OXFORD [ OXFORD SEMICONDUCTOR ]
