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OXCFU950_07 参数 Datasheet PDF下载

OXCFU950_07图片预览
型号: OXCFU950_07
PDF下载: 下载PDF文件 查看货源
内容描述: USB / UART多功能16位PC卡设备 [USB/UART multi-function 16-bit PC Card device]
分类和应用: PC
文件页数/大小: 74 页 / 446 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OXCFU950 DATA SHEET  
OXFORD SEMICONDUCTOR, INC.  
Pin Number  
Pad TypeNote 1  
Pin Name  
Description  
is enabled, upon de-assertion of the DSR# pin, the transmitter completes  
the current character & enters idle mode until the DSR# pin is  
reasserted. Note: flow control characters are transmitted regardless of  
the state of the DSR# pin.  
57  
1
I_C_33_5_N_  
P_33  
RI#  
Active-low modem ring-indicator input.  
Power supply to UART and MIO I/O interfaces. Voltage on these pins  
should be tied to 1.8 V to 3.3 V supply (depending on requirement).  
UART_VDD3V3  
Crystal Oscillator / PLL pinsNote4  
51  
50  
A_18  
A_18  
XTLO  
XTLI  
Crystal oscillator output.  
Crystal oscillator input. Frequency = 12 MHz.  
Note : a pull-down resistor of 500 KΩ is required on this pin.  
Ground (0 Volts) for PLL & oscillator cells. This pin should be tied to  
ground.  
Power supply for PLL & oscillator cells. This pin should be tied to 1.8  
volts (i.e. tied to REG_VDD1V8 pin).  
49  
48  
P_18  
P_18  
PLL_VSS1V8  
PLL_VDD1V8  
USBNote 5  
2
3
4
A_33  
A_33  
P_33  
USB_DP  
USB_DM  
USB_VDD3V3  
USB data plus.  
USB data minus.  
Power supply to USB I/O interface. This pin should be tied to 3.3 volts.  
Multi-Purpose I/ONote 3  
64,63,62,61  
B_T_33_5_N_1_ MIO[3:0]  
Multipurpose IO pins.  
Note: if enabled, MIO[3:0] can be used as an interrupt inputs.  
MIO[3:2] can be configured to act as the USB power management  
control signals PORT_OVER_CURRENT & PORT_POWER  
Miscellaneous Pins/PadsNote2  
52  
20  
I_C_33_5_N_U  
I_C_33_5_N_D  
CIS_MODE  
TEST  
Test mode select pin/default CIS select. (See Section 5.1)  
Test pin. This pin should be tied to VSS for normal operation.  
Additional Power and Ground  
65 (Thermal bonding P_00  
pad)  
VSS  
Main digital ground pin. The VSS pin should be tied to ground. Note this  
is the thermal bonding pin underneath the 64-pin QFN package  
Output supply from internal voltage regulator at 1.8 V. Can be used as  
power supply to PLL (i.e. pin #48).  
27  
P_18  
REG_VDD1V8  
Table 1: Pin Descriptions  
Note 1 : Pad syntax description  
Pad type  
syntax  
Digital Input pad  
Digital Output pad  
Digital Tristate output pad  
Digital Bidirectional pad  
Analogue pad  
t_a_xy_h_i_p  
t_a_xy_d  
t_a_xy_d  
t_a_xy_h_i_d_p  
t_xy  
t_xy  
Power Pad  
Table 2: Pad Type Syntax  
DS-0023 February 2007  
External—Free Release  
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