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OXCF950-TBBG 参数 Datasheet PDF下载

OXCF950-TBBG图片预览
型号: OXCF950-TBBG
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本异步16位PC卡或CF卡UART设备 [low cost asynchronous 16-bit PC card or Compact Flash UART device]
分类和应用: PC
文件页数/大小: 66 页 / 362 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
 浏览型号OXCF950-TBBG的Datasheet PDF文件第5页浏览型号OXCF950-TBBG的Datasheet PDF文件第6页浏览型号OXCF950-TBBG的Datasheet PDF文件第7页浏览型号OXCF950-TBBG的Datasheet PDF文件第8页浏览型号OXCF950-TBBG的Datasheet PDF文件第10页浏览型号OXCF950-TBBG的Datasheet PDF文件第11页浏览型号OXCF950-TBBG的Datasheet PDF文件第12页浏览型号OXCF950-TBBG的Datasheet PDF文件第13页  
OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
28 (E5)
I
DSR#
the transmitter will complete the current character and enter
the idle mode until the CTS# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the CTS# pin.
Active-low modem data-set-ready input. If automated DSR#
flow control is enabled, upon de-assertion of the DSR# pin,
the transmitter will complete the current character and enter
the idle mode until the DSR# pin is reasserted. Note: flow
control characters are transmitted regardless of the state of
the DSR# pin
External receiver clock for isochronous applications. The
Rx_Clk_In is selected when register CKS[1:0] = ’01’
Active-low modem Ring-indicator input
External transmitter clock. This clock can be used by the
transmitter (and indirectly by the receiver) when register
CKS[6] = ‘1’.
Crystal oscillator output
Crystal oscillator input or external clock pin. Frequency
1.8MHz -> 60MHz.
For 1.8 to 20 MHz, a crystal may be used. Above this range,
an external clock source is required.
Local Bus Mode
: Active low local bus Chip select
C950 Mode:
Active low OUT1
Normal Mode
: Address bit 5
Local Bus Mode
: Active-low local bus read enable
C950 Mode:Active
low RXRDY
Normal Mode
: Address bit 6
Local Bus Mode
: Active-low local bus write enable
C950 Mode:Active
low TXRDY
Normal Mode
: Address bit 7
Local Bus Mode
: Active high local bus Reset
C950 Mode:Active
low OUT2
Normal Mode :
Address bit 4
EEPROM clock. In normal operation the frequency of this is
XTLI input clock / 64. The clock is only active during
configuration following reset.
EEPROM active-high Chip Select.
EEPROM data in. This pin should be pulled up using 1-10k
resistor if an EEPROM is used, or pulled up/down depending
upon required stand-alone mode..
EEPROM data out.
User defined IO pins.
Note: that if enabled, MIO[1:0] can be used as an interrupt
inputs.
Local Bus mode select. Note Local Bus mode requires
indirect addressing, which is only supported by the PCMCIA
specification
‘0’ = Normal Mode (CF/PCMCIA compatible)
‘1’ = Local Bus Mode (PCMCIA compatible)
Ground (0 Volts). The GND pins should be tied to ground
Page 9 of 66
Rx_Clk_In
30 (D5)
I
RI#
Tx_Clk_In
21 (F4)
20 (H4)
O
I
XTLO
XTLI
34 (C6)
35 (C4)
36 (B6)
33 (E4)
EEPROM
13 (H1)
14 (G2)
16 (G3)
15 (H2)
Miscellaneous Pins
18, 31
(G4, D6)
17 (H3)
O
O
I
O
O
I
O
O
I
O
O
I
O
O
I
O
I/O
I
LBCS#
OUT1#
A[5]
LBRD#
2
RXRDY#
A[6]
LBWR#
TXRDY#
A[7]
LBRST
2
OUT2#
A[4]
EE_CK
EE_CS
EE_DI
EE_DO
MIO[1:0]
MODE
Power and Ground
2
39, 19, 8
(A5, E3, D3)
DS-0027 Feb 06
G
GND
External—Free Release