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OXCF950 参数 Datasheet PDF下载

OXCF950图片预览
型号: OXCF950
PDF下载: 下载PDF文件 查看货源
内容描述: 单个全双工异步信道128字节深度的发送器/接收FIFO中 [Single full-duplex asynchronous channel 128-byte deep transmitter / receiver FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 66 页 / 789 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OXCF950 rev B DATA SHEET V 1.0  
OXFORD SEMICONDUCTOR LTD.  
PINDESCRIPTIONS  
3
TQFP Pin Number (TFBGA ball)  
CF/PCMCIA Interface and Control  
46, 45, 43, 42  
(D4, A2, A3, B3)  
6, 7, 10, 11, 12, 37, 38, 41  
Dir1  
I
Name  
A[3:0]  
D[7:0]  
Description  
PCMCIA/CF address bus, bits [3:0]  
PCMCIA/CF data bi-directional bus.  
I/O  
(E2, E1, F1, F3, G1, A6, B5, A4)  
44 (C3)  
5 (D1)  
4 (D2)  
1 (B1)  
IU  
IU  
I
REG#  
CE[1]#  
OE#  
Register select and I/O enable  
Active low card enable  
Active low memory read enable  
Active-low write enable used for strobing Memory Write data  
(Attribute memory).  
I
WE#  
3 (C1)  
2 (C2)  
32 (C5)  
IU  
IU  
O
IORD#  
IOWR#  
WP  
Active-low I/O read enable  
Active-low I/O write enable  
Write protect (in Memory only mode)  
O
IOIS16#  
Data is 16 bit (in IO and Memory mode)  
O
IU  
O
INT  
RESET  
READY#  
C950 Mode:Active-high interrupt request  
PCMCIA/CF Reset  
Device ready (in Memory only mode)  
47 (B2)  
48 (A1)  
IREQ#  
SOUT  
Active-low Interrupt request (in C950, IO and Memory mode).  
UART serial data output.  
UART / Local Bus Function  
24 (H6)  
O
I
IrDA_Out  
SIN  
UART IrDA data output when MCR[6] is set in enhanced  
mode.  
UART serial data input.  
23 (G5)  
IrDA_In  
UART IrDA data input when IrDA mode is enabled (see  
above).  
29 (E6)  
26 (F5)  
I
O
DCD#  
DTR#  
Active-low modem data-carrier-detect input.  
Active-low modem data-terminal-ready output. If automated  
DTR# flow control is enabled, the DTR# pin is asserted and  
de-asserted if the receiver FIFO reaches or falls below the  
programmed thresholds, respectively.  
485_En  
In RS485 half-duplex mode, the DTR# pin may be  
programmed to reflect the state of the transmitter empty bit to  
automatically control the direction of the RS485 transceiver  
buffer (see register ACR[4:3]).  
Tx_Clk_Out  
RTS#  
Transmitter 1x clock (baud rate generator output). For  
isochronous applications, the 1x (or Nx) transmitter clock may  
be asserted on the DTR# pin (see register CKS[5:4]).  
Active–low modem request-to-send output. If automated  
RTS# flow control is enabled, the RTS# pin is de-asserted  
and reasserted whenever the receiver FIFO reaches or falls  
below the programmed thresholds, respectively.  
25 (G6)  
27 (F6)  
O
I
CTS#  
Active-low modem clear-to-send input. If automated CTS#  
flow control is enabled, upon de-assertion of the CTS# pin,  
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