OXFORD SEMICONDUCTOR LTD.
OX16PCI952
4
P
IN
D
ESCRIPTION
Please refer to Section “Pin Information” for actual Signal Name to Pin Number assignments.
Pins
PCI interface
2, 5, 6, 7, 8, 12, 13, 14, 15,
32, 33, 34, 35, 36, 39, 40, 41,
43, 44, 47, 48, 49, 50, 51, 52,
121, 122, 123, 124, 125, 126,
127
3, 16, 31, 42
117
17
24
18
23
25
28
27
26
4
115
113
114
120
Serial port pins
88
Dir
1
P_I/O
Name
AD[31:0]
Description
Multiplexed PCI Address/Data bus
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
I
C/BE[3:0]#
PCI CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA#,
INTB#
PME#
FIFOSEL
PCI Command/Byte enable
PCI system clock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialization device select
PCI system reset
PCI interrupts
Power management event
FIFO select.
For backward compatibility with 16C550, 16C650 and
16C750 devices the FIFO depth of both UARTs is 16 when
FIFOSEL is low. The FIFO size of both UARTs is increased
to 128 when FIFOSEL is high.
The FIFO size of each UART may also be set to 128 by
setting the UARTs FCR[5] when LCR[7] is set, or by putting
the device into enhanced mode.
The unlatched state of this pin is readable by software.
Serial data output, Uart 0
Serial data output, Uart 1.
UART IrDA data outputs, for UART 0 and 1.
Serial data output pins redefined as IrDA data outputs when
MCR[6] of the corresponding UART channel is set in
enhanced mode
Serial data input, UART 0.
Serial data input, UART 1.
UART IrDA data inputs, for UART 0 and 1.
Serial data input pins redefined as IrDA data inputs when
MCR[6] of the corresponding UART channel is set in
enhanced mode
111
101
111
101
104
94
104
94
O
O
O
O
I
I
I
I
EXT_DATA_OUT[0]
EXT_DATA_OUT[1]
IrDA_Out[0]
IrDA_Out[1]
EXT_DATA_IN[0]
EXT_DATA_IN[1]
IrDA_In[0]
IrDA_In[1]
DS-0028 Jul 05
External-Free Release
Page
9
OXFORD [ OXFORD SEMICONDUCTOR ]
