OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
PERFORMANCE COMPARISON
1
Feature
OX16C954
4
16C454
4
16C554
4
16C654
4
16C750
1
Integrated Serial channels
Good-Data status
Yes
No
No
115 kbps
n/a
1
No
No
115 kbps
n/a
16
No
No
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Yes
No
No
15 Mbps
60 Mbps
128
1.5 Mbps
n/a
64
1 Mbps
n/a
64
Sleep mode
Yes
No
No
No
No
1
No
No
No
No
4
Yes
Yes
Yes
No
Yes
No
Auto Xon/Xoff flow
Yes
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Yes
Yes
No
Yes
128
4
4
128
1
1
4
1
128
n/a
No
n/a
n/a
n/a
No
No
No
No
No
No
n/a
No
No
No
n/a
No
No
No
No
No
No
4
n/a
No
Yes
No
Yes
No
No
Yes
No
No
248
2
n/a
No
Yes
No
Software reset
Yes
No
No
Device ID
Yes
No
No
9-bit data frames
Yes
No
No
RS485 buffer enable
Infra-red (IrDA)
Yes
No
No
Yes
Yes
No
Table 1 OX16C954 performance compared with 16C454, 16C554, 16C654 and 16C750 devices
Improvements of the OX16C954 over previous generations of PC UARTs:
Automatic flow control:
Deeper FIFOs:
The OX16C954 offers 128-byte deep FIFOs for the
transmitter and receiver.
The UART automatically handles either or both in-band
(software) flow control (transmitting and receiving Xon/Xoff
characters) and out-of-band (hardware) flow control using
the RTS#/CTS# or DSR#/DTR# modem control lines.
Higher data rates:
Transmission and reception baud rates up to 15Mbps. A
flexible clock prescaler offers division ratios of 1 to 31 7/8
in steps of 1/8 using a divide-by-“M N/8” circuitry. The
flexible prescaler allows users to select from a wide variety
of input clock frequencies as well as access to higher baud
rates whilst maintaining compatibility with existing software
drivers (see section 14.2).
Special character detection:
The receiver can be programmed to generate an interrupt
upon reception of a particular character value.
Power-down:
The device can be placed in ‘sleep mode’ to conserve
power
External clock option:
The receiver can accept an external clock on the DSR#
input. The transmitter can accept a 1x clock on the RI#
input and/or assert its own (Nx) clock on the DTR# output.
In 1x mode, asynchronous data may be transmitted and
received at speeds up to 60 Mbps (see section 14.6).
Readable FIFO levels:
Driver efficiency can be improved by using readable FIFO
levels.
Selectable trigger levels:
The receiver FIFO threshold can be arbitrarily
programmed. The transmitter FIFO threshold and
DS-0026 Jun 05
External—Free Release
Page 5
OXFORD [ OXFORD SEMICONDUCTOR ]
