TransDimension Inc.
Interfacing OTG243 to Motorola MCF5272 ColdFire Processor
Bus Control:
/CS, /RD,
and
/WR
In this reference design, the OTG243 is accessed through MCF5272’s
nCS2
(base memory
address 40000000). Thus OTG243 chip select
/CS,
read strobe
/RD,
and write strobe
/WR
should be tied to
nCS2, nOE/RD,
and
R/nW
of the MCF5272, respectively.
Address Bus:
A
8
:A
2
The OTG243 address bus
A
8
:A
2
is connected to
A8:A2
of the MCF5272.
Data Bus:
D
31
:D
0
The lower 16-bit data bus of the OTG243
D
15
:D
0
should be connected to
D
31
:D
16
of the
MCF5272. This is due to MCF5272 data bus
D
15
:D
0
becoming GPIO port C when configured as
16-bit external data bus. The upper 16-bit data bus of the OTG243
D
31
:D
16
should be pull-down
with 15K resistors.
Hardware Reset:
/RESET
For many applications, the OTG243
/RESET
can be tied to MCF5272’s system reset (nRSTI or
nRSTO).
However, it is recommended that a MCF5272 GPIO pin be allocated as the OTG243
hardware reset for flexibility of user software.
In this reference design,
PC12
(GPIO Port C bit 12) of the MCF5272 is assigned to the
OTG243’s
/RESET,
and its selection depends on the application. To improve reliability, a pull-
up resistor is desired. An RC filter circuit is highly recommended to eliminate unexpected noise
triggered reset.
Interrupt:
INT
The interrupt signal
INT
generated by the OTG243 must be tied to one of the six
nINTn
pins of
the MCF5272. In this reference design, MCF5272 pin
nINT2
is employed, and its selection
again depends on the application.
Note that the active level (active high or active low) and the output type (totem-pole or wired
OR) of the OTG243
INT
pin are programmable. For this reference design, the OTG243
INT
pin
is to be programmed to active low, totem-pole operation. A pull-up resistor is recommended.
4
OXFORD [ OXFORD SEMICONDUCTOR ]
