Figure 8. 16-digit parallel I/O
Vcc
GND
D0–D6
2
Control
8080
P
System
Data
0
1
2
3
4
5
6
7
Display Display Display Display
D15
D0
WR
WR
WR
WR
I/O or Memory Mapped Addressing
Some designers may wish to avoid the additional cost of a par-
allel l/O in their system. Structuring the addressing architecture
for the DLX1414 to look like a set of peripheral or output
devices (I/O mapped) or RAMs and ROMs (memory mapped),
is very easy. Figure 9 shows the simplicity of interfacing to
microprocessors, such as 8080, Z80 and 6502 as examples.
The interface with the 6800 microprocessor in Figure 10 illus-
trates the need for designers to check the timing requirements
of the DLX1414 and the LP. The typical data output hold time is
only 30 ns for DBE=02 timing; two inverters in the DBE line are
added to increase the data output hold time for compatibility
with the 50 ns minimum spec of the DLX1414.
Figure 9. Mapped interface
Re s et
Int
H ol d
Wa i t
Optio nal
B u ffer s
Por t A 0–6
A0
A1
A2
A3
Po r t B
A
B
7442
C
D
3
2
1
0
WR
8255
Figure 8 illustrates a 16-character display with an 8080 system
using the 8255 programmable peripheral interface I/O device.
The following program will display a simple 16 character mes-
sage using this interface.
Program for 16-Character Message
INT:
MVI A,80H
OUT CON-
TROLMVI B,00H
LXI H, TABLE
MOV A,M
OUT PORTA
MOV A, B
CALL DSPWT
INX H
INR B
MVI A, 10H
CMP B
JNZ DISP1
HALT
DSPWT: ORI F0H
OUT PORTB
ANI 7FH
OUT PORTB
ORI F0H
OUT PORTB
RET
TABLE:
DL
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
;CONTROL DATA MODE 0
;LOAD CONTROL REGISTER
;SET COUNTER =0
;SET TABLE ADDRESS
;MOVE TABLE DATA TO
ACCUMULATOR
;LOAD DATA PORT
;LOAD ADDRESS AND CONTROL
;INCREMENT TABLE ADDRESS
;INCREMENT COUNTER
;SET # OF DIGITS
;16 CHARACTERS ?
;END OF PROGRAM
;SET CONTROL BITS OFF
;LOAD CONTROL
;SET WRITE BIT ON
;LOAD WRITE
;SET WRITE BIT OFF
;LOAD CONTROL
;0C3H
;0C9H
;0D4H
;0D3H
;0C1H
;0D4H
;0CEH
;0C1H
;0C6H
;0A0H
;0D3H
;0D4H
;0C8H
;0C7H
;0C9H
;0CCH
Address
8080
Z80
6502
D ata
Ad dr ess
D ata
OSC
Control
DISP:
DISP1:
D i s p l ay Di s play D isplay D isp lay
D15
D0
Data 0-6
A0
A1
0
A
1
B
Decoder
2
C
3
D
A2
A3
Dis play
Se lect
WR
Figure 10. Gating the write pulse
Reset
NMI
Halt
IRQ
TSC
Data
6800 Address
0
1
0
2
DBE
Data
Address
H1
H2
Clock
Driver
BA
VMA
R/W
Decoder
Display
Display
Display
Display
A0
,
A1
D0
–
D7
CE CE
Conclusion
Although other manufacturers’ products are used in examples, this
application note does not imply specific endorsement, or recom-
mendation or warranty of other manufacturer’s products by Infineon
/ OSRAM.
The interface schemes shown demonstrate the simplicity of
using the DLX1414 with microprocessors. The slight differences
encountered with different microprocessors to interface with
the DLX1414 are similar to those encountered when using dif-
ferent RAMs The techniques used in the examples were shown
for their generality. The user will undoubtedly invent other
schemes to optimize his particular system to its requirements.
Appnote 15
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
4
May 31, 2000-12
OSRAM [ OSRAM GMBH ]
