DLR3416, DLO3416, DLG3416
Loading Data
Setting the chip enable (CE1, CE2, CE3, CE4) to their
true state will enable loading. The desired data code
(D0-D6) and digit address (A0, A1) must be held stable
during the write cycle for storing new data.
Data entry may be asynchronous and random. Digit 0 is
defined as right hand digit with A1=A2=0.
To clear the entire internal four-digit memory hold the
clear (CLR) low for 1.0 ms. All illuminated dots will be
turned off within one complete display multiplex cycle,
1.0 ms minimum. The clear function will clear both the
ASCII RAM and the cursor RAM.
Loading Cursor
Setting the chip enables (CE1, CE2, CE3, CE4) and
cursor select (CU) to their true state will enable cursor
loading. A write (WR) pulse will now store or remove a
cursor into the digit location addressed by A0, A1, as
defined in data entry. A cursor will be stored if D0=1 and
will removed if D0=0. The cursor (CU) pulse width should
not be less than the write (WR) pulse or erroneous data
may appear in the display.
If the cursor is not required, the cursor enable signal
(CUE) may be tied low to disable the cursor function. For
a flashing cursor, simply pulse CUE. If the cursor has
been loaded to any or all positions in the display, then
CUE will control whether the cursor(s) or the characters
will appear. CUE does not affect the contents of cursor
memory.
Display Blanking
Blank the display by loading a blank or space into each
digit of the display or by using the (BL) display blank input.
Setting the (BL) input low does not affect the contents of
either data or cursor memory. A flashing display can be
achieved by pulsing (BL). A flashing circuit can be
constructed using a 555 a stable multivibrator. Figure 4
illustrates a circuit in which varying R2 (100K~10K) will
have a flash rate of 1.0 Hz~10 Hz.
The display can be dimmed by pulsing (BL) line at a
frequency sufficiently fast to not interfere with the internal
clock. The dimming signal frequency should be 2.5 kHz or
higher. Dimming the display also reduces power
consumption.
An example of a simple dimming circuit using a 556 is
illustrated in Figure 5. Adjusting potentiometer R3 will dim
the display by changing the blanking pulse duty cycle.
Design Considerations
For details on design and applications of the DLX3416
using standard bus configurations in multiple display
systems, or parallel I/O devices, such as the 8255 with an
8080 or memory mapped addressing on processors such
as the 8080, Z80, 6502, or 6800, refer to Appnote 17 at
www.osram-os.com
DLX3416—Flashing Circuit Using a 555 and
Flashing (Blanking) Timing
V
CC
= 5 V
1
8
4.7 k
Ω
R
1
2
To BL
Pin on
Display
555
Timer
3
7
100 k
Ω
6
R
2
C
3
4
5
C
4
0.01 µF
10 µF
IDCD5033
1
0
~500 ms
~
Blanking Pulse Width
~
~
~ 2 Hz Blanking Frequency ~ 50% Duty Factor
IDCD5035
DLX3416—Dimming Circuit Using a 556 and
Dimming (Blanking) Timing
V
CC
= 5 V
47 k
Ω
Dimming (Blanking)
Control
1
14
500 k
Ω
R
2
R
3
R
1
200
Ω
2
13
C
3
1000 pF
3
12
556
11
Dual Timer
10
To BL Pin
on Display
C
2
0.01 µF
4
C
4
0.01 µF
5
6
9
C
1
4700 pF
7
8
IDCD5034
1
0
~
~ 200 µs
~ 5 kHz Blanking Frequency
~
Blanking Pulse Width
4 µs min., 196 µs max.
IDCD5036
2006-01-23
8
OSRAM [ OSRAM GMBH ]
