Page No. : 5/7
High/Low Voltage Power Compensation
The current flowing by the power BJT has an extra value
Δ
I
=
V
IN
×
T
D
due to the system delay T
D
that the current
L
P
detected from the sense pin to power BJT cut off in the RS2030 (Among these, V
IN
is the primary winding voltage of
the transformer and L
P
is the primary wind inductance,
V
IN
ranges from 85VAC to 264VAC.) To guarantee the output
power is a constant for universal input AC voltage, there is a dynamic peak limit circuit to compensate the system
delay T
D
that the system delay brings on.
Soft Start
The VDD pin of the RS2030 is the power supply voltage pin and the feedback pin, so the duty cycle will be increase
with VDD voltage decreasing. The soft start performance have been implemented by increasing the duty cycle in
starting.
Leading-edge Blanking (LEB)
Each time the power BJT is switched on, a turn-on spike will inevitably occur at the sense pin, which would disturb the
internal signal from the sampling of the R
SENSE
. There is a 250n sec leading edge blanking time built in to avoid the
effect of the turn-on spike and the power BJT cannot be switched off during this time. So that the conventional
external RC filtering on sense input is no longer required.
Short Circuit Protection (SCP)
When the output circuit is shorted, the restart time of the RS2030 and the input power will be increased with input
voltage increasing, then the power NPN BJT will be hot and destroyed. So the Chip-Rail secondary delay circuit has
been introduced for decrease the restart time.
TO-92 Dimension
α
2
DIM
A
B
C
D
E
F
G
H
I
α1
α2
α3
Min.
4.33
4.33
12.70
0.36
-
3.36
0.36
-
-
-
-
-
Max.
4.83
4.83
-
0.56
*1.27
3.76
0.56
*2.54
*1.27
*5°
*2°
*2°
A
B
1
2
3
α
3
C
D
H
I
E
3-Lead TO-92 Plastic Package
Package Code: A
G
*: Typical, Unit: mm
α
1
F
DS-RS2030X-EN-V1 Dec, 2007
www.Orister.com
ORISTER [ ORISTER CORPORATION ]
