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Functional Description
1. Startup
This device includes a high voltage start up current source connected on the SW of the device. As soon as a voltage is applied on the input of
the converter, this start up current source is activated and to charge the VCC capacitor as long as VCC is lower than VSTART. When reaching
VSTART, the start up current source is cut off by UVLO&TSD and the device begins to operate by turning on and off its main power MOSFET.
As the COMP pin does not receive any current from the opto-coupler, the device operates at full current capacity and the output voltage rises
until reaching the regulation point where the secondary loop begins to send a current in the opto-coupler. At this point, the converter enters a
regulated operation where the COMP pin receives the amount of current needed to deliver the right power on secondary side.
Fig 1 Startup circuit
2. Feedback
A feedback pin controls the operation of the device. Unlike conventional PWM control circuits which use a voltage input, the COMP pin is
sensitive to current.
Figure 2
presents the internal current mode structure. The Power MOSFET delivers a sense current which is proportional to
the main current. R2 receives this current and the current coming from the COMP pin. The voltage across R2 VR2 is then compared to a fixed
reference voltage. The MOSFET is switched off when VR2 equals the reference voltage.
3. Leading Edge Blanking (LEB)
At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by the primary side
capacitance and secondary side rectifier diode reverse recovery. Excessive voltage across the sense resistor would lead to false feedback
operation in the current mode PWM control. To counter this effect, the device employs a leading edge blanking (LEB) circuit. This circuit inhibits
the PWM comparator for a short time (typically 500ns) after the Sense FET is turned on.
4. Under Voltage Lock Out
Once fault condition occurs, switching is terminated and the Sense FET remains off. This causes VCC to fall. When VCC reaches the UVLO
stop voltage, 8V, the protection is reset and the internal high voltage current source charges the VCC capacitor. When VCC reaches the UVLO
start voltage, 14.5V, the device resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of
the power Sense FET until the fault condition is eliminated.
5. Thermal Shutdown (TSD)
The Sense FET and the control IC are integrated in the same chip, making it easier for the control IC to detect the temperature of the Sense
FET. When the temperature exceeds approximately 170°C, thermal shutdown is activated, the device turn off the Sense FET and the high
voltage current source to charge VCC. The device will go back to work when the lower threshold temperature about 140°C is reached.
6. Over Voltage Protection (OVP)
In case of malfunction in the secondary side feedback circuit, or feedback loop open caused by a defect of solder, the current through the opto-
coupler transistor becomes almost zero. Because excess energy is provided to the output, the output voltage may exceed the rated voltage,
resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is
employed. If VCC exceeds 42V, OVP circuit is activated resulting in termination of the switching operation. In order to avoid undesired activation
of OVP during normal operation, VCC should be properly designed to be below 42V.
DS-RS2022-02
November,
2010
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ORISTER [ ORISTER CORPORATION ]
