MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flip–flops share common clock and reset inputs.
The reset is active low, and independent of the clock.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14174BCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
14174B
AWLYWW
1
•
•
•
•
•
Static Operation
All Inputs and Outputs Buffered
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
•
Functional Equivalent to TTL 74174
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
–0.5 to +18.0
–0.5 to V
DD
+ 0.5
±10
500
–55 to +125
–65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
A
WL, L
YY, Y
WW, W
SOEIAJ–16
F SUFFIX
CASE 966
16
MC14174B
ALYW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC14174BCP
MC14174BD
MC14174BDR2
MC14174BF
MC14174BFEL
Package
PDIP–16
SOIC–16
SOIC–16
SOEIAJ–16
SOEIAJ–16
Shipping
2000/Box
48/Rail
2500/Tape & Reel
See Note 1.
See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2000
1
August, 2000 – Rev. 4
Publication Order Number:
MC14174B/D
ONSEMI [ ON SEMICONDUCTOR ]
