KAI−04070
Physical Description
Pin Description and Device Orientation
V3T
V1T VDDc GND
Rc
H2SLc H1Bc H2Sc R2cd H2Sd H1Bd H2SLd Rd
GND VDDd V1T
V3T
65 63 61 59 57 55 53 51 49 47
43 41 39 37
67
45
35
ESD V4T
V2T
VOUTc RDcd OGc
H2Bc H1Sc SUB
H1Sd H2Bd
OGd RDcd VOUTd V2T
V4T
DevID
68 66 64 62 60 58 56 54 52 50 48
44 42 40 38
46
36
Pixel (1,1)
4
6
V2B
5
8
10 12 14 16 18 20 22
24 26 28 30 32 34
V4B
VOUTa RDab OGa H2Ba H1Sa
H1Sb H2Bb
RDab
V2B V4B
SUB
OGb
VOUTb
ESD
33
1
3
7
9
11 13 15 17 19 21
23 25 27 29 31
V3B
V1B
VDDa GND
Ra
H2SLa H1Ba H2Sa R2ab H2Sb H1Bb
Rb
GND VDDb V1B
H2SLb
V3B
Figure 5. Package Pin Designations − Top View
Table 4. PACKAGE PIN DESCRIPTION
Pin
1
Name
V3B
Description
Vertical CCD Clock, Phase 3, Bottom
Vertical CCD Clock, Phase 1, Bottom
Vertical CCD Clock, Phase 4, Bottom
Output Amplifier Supply, Quadrant a
Vertical CCD Clock, Phase 2, Bottom
Ground
3
V1B
4
V4B
5
VDDa
V2B
6
7
GND
VOUTa
Ra
8
Video Output, Quadrant a
9
Reset Gate, Standard (High) Gain, Quadrant a
Reset Drain, Quadrants a & b
10
11
12
13
14
15
16
17
18
19
20
21
RDab
H2SLa
OGa
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
Output Gate, Quadrant a
H1Ba
H2Ba
H2Sa
H1Sa
R2ab
SUB
Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
Horizontal CCD Clock, Phase 2, Storage, Quadrant a
Horizontal CCD Clock, Phase 1, Storage, Quadrant a
Reset Gate, Low Gain, Quadrants a & b
Substrate
H2Sb
H1Sb
H1Bb
Horizontal CCD Clock, Phase 2, Storage, Quadrant b
Horizontal CCD Clock, Phase 1, Storage, Quadrant b
Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
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