FS6322-04
Three-PLL Clock Generator IC
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
CLOCK
(MHz)
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Clock Output (CLK_X)
Crystal oscillator derived outputs
Measured @1.4V; CL = 20pF
Duty Cycle *
43
45
51
51
57
55
%
%
PLL derived outputs
Measured @1.4V; CL = 20pF
Duty Cycle *
Rise Time *
Fall Time *
tr
tf
VO = 0.4V to 2.4V; CL = 20pF
VO = 2.4V to 0.4V; CL = 20pF
2.2
1.8
ns
ns
From rising edge to next rising edge at VDD/2, CL =
20pF
Jitter, Period (RMS) *
50
ps
ps
tj(1σ)
tj(∆P)
From rising edge to next rising edge at VDD/2, CL =
20pF
Jitter, Period (peak-peak) *
400
PLL-derived outputs
Jitter, Cumulative (RMS)*
Phase Noise *
tj(LT)
100
-80
ps
From 0-500µs at VDD/2, CL = 20pF
compared to ideal clock source
PLL derived outputs
@ 100KHz offset from fundamental
dbC/Hz
5
3.1.02
ONSEMI [ ONSEMI ]
