FEDL9261A-01
OKI Semiconductor
ML9261A
AC Characteristics-1
(V
DD
= 4.5 to 5.5 V, V
DISP
= 20 to 60 V, Ta = –40 to +85°C)
Parameter
CLK Pulse Width
DIN Setup Time
DIN Hold Time
CLK-LS Setup Time
LS-CLK Setup Time
CLK-LS Hold Time
LS-CHG Setup Time
LS-CL Setup Time
LS Pulse Width
CHG Pulse Width
CL
Pulse Width
DOUT Delay time
Driver Output Delay Time
Symbol
t
W
(CLK)
t
SU
(D-CLK)
t
H
(CLK-D)
t
SU
(CLK-LS)
t
SU
(LS-CLK)
t
SU
(L-CLK)
t
H
(CLK-L)
t
SU
(LS-CHG)
t
SU
(LS-CL)
t
W
(LS)
t
W
(CHG)
t
W
(CL)
t
PD
, t
PRD
t
DLH
t
DHL
t
DRHL
t
TLH
Driver Output Slew Rate
t
THL
Condition
—
—
—
—
During normal operation
At display data reset
At display data reset
—
—
—
—
—
Load: 30 pF
V
DISP
= 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance
V
DISP
= 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance
Min.
80
50
50
50
50
50
50
50
50
80
10
10
—
—
—
—
—
—
Max.
150
—
—
—
—
—
—
—
—
—
—
—
50
2.0
2.0
2.0
5.0
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
µs
µs
µs
µs
µs
AC Characteristics-2
(V
DD
= 3.0 to 3.6 V, V
DISP
= 20 to 60 V, Ta = –40 to +85°C)
Parameter
CLK Pulse Width
DIN Setup Time
DIN Hold Time
CLK-LS Setup Time
LS-CLK Setup Time
CLK-LS Hold Time
LS-CHG Setup Time
LS-CL Setup Time
LS Pulse Width
CHG Pulse Width
CL
Pulse Width
DOUT Delay time
Driver Output Delay Time
Symbol
t
W
(CLK)
t
SU
(D-CLK)
t
H
(CLK-D)
t
SU
(CLK-LS)
t
SU
(LS-CLK)
t
SU
(L-CLK)
t
H
(CLK-L)
t
SU
(LS-CHG)
t
SU
(LS-CL)
t
W
(LS)
t
W
(CHG)
t
W
(CL)
t
PD
, t
PRD
t
DLH
t
DHL
t
DRHL
t
TLH
Driver Output Slew Rate
t
THL
Condition
—
—
—
—
During normal operation
At display data reset
At display data reset
—
—
—
—
—
Load: 30 pF
V
DISP
= 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance
V
DISP
= 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance
Min.
80
50
50
50
50
50
50
50
50
80
10
10
—
—
—
—
—
—
Max.
150
—
—
—
—
—
—
—
—
—
—
—
50
3.0
3.0
3.0
5.0
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
µs
µs
µs
µs
µs
8/16
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