FEDL9226-01
OKI Semiconductor
ML9226
PIN DESCRIPTIONS
Pin
1, 64
10
33
30
41
50 to 63,
65 to 67,
69 to 71,
73, 74
75, 76,
78 to 80,
2 to 6
7, 8, 9
36
GRID1
to
3
CS
O
I
SEG23 to 32
O
Symbol
V
DISP
D-GND
L-GND
V
CC
V
REG
Type
—
—
—
O
O
Power supply pins.
Pin1 and pin64 should be connected externally.
D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for
the logic circuit. Pins 10 and 33 should be connected externally.
5 V output pin for internal logic portion and external logic circuit.
Reference voltage (5 V) output pin for A/D converter.
Segment (anode) signal output pins for a VFD tube.
SEG1 to 22
O
These pins can be directly connected to the VFD tube. External circuit is
not required. I
OH
≤
–5 mA
Segment (anode) signal output pins for a VFD tube.
These pins can be directly connected to the VFD tube. External circuit is
not required. I
OH
≤
–10 mA
Inverted Grid signal output pins.
For pre-driver, the external circuit is requiend. I
OL
≤
10 mA
Chip Select input pin.
Data input/output operation is valid when this pin is set at a High level.
Serial clock input pin.
35
CLOCK
I
Data is input and/or output through the DATA I/O pin at the rising edge of
the serial clock.
Serial data input/output pin.
34
DATA I/O
I/O
Data is input to/comes out from the shift register at the rising edge of the
serial clock.
Interrupt signal output to microcontroller. When any key of key matrix is
pressed or released, key scanning is started. After the completion of the
one cycle, this pin goes to high level and keeps the high level until
keyscan stop mode is selected.
Duplex/Triplex operation select input pin.
29
42 to 49
21 to 26
DUP/TRI
CH1 to 8
A1 to A3
B1 to B3
COL1
to
5
I
I
I
Duplex (1/2 duty) operation is selected when this pin is set at a V
CC
level.
Triplex (1/3 duty) operation is selected when this pin is set at a GND level.
Analog voltage input pin for the 8-bit A/D converter.
Input pin for the encoder type rotary switch. The phase of an An/Bn input
is detected.
Return inputs from the key matrix.
16 to 20
I
These pins are active low. When key matrix are in the inactive sate, these
pins are at high level through the internal pull-up resistors. All the inputs
do not have the cahttering absorption function for the keyscans.
Key switch scanning outputs.
11 to 15
ROW1 to 5
O
Normally low level is output through these pin. When any switch of key
matrix is depressed or released, key scanning is started and is continued
until keyscan stop mode is selected. When keyscan stop mode is
selected, all outputs of ROW1 to 5 go back to low level.
Description
27
INT
O
4/26
OKI [ OKI ELECTRONIC COMPONETS ]
