¡ Semiconductor
ML9052
Display data RAM
• Display data RAM
This is the RAM storing the dot data for display and has an organization of 97 (12 pages ¥ 8 bits
+1) ¥ 132 bits. It is possible to access any required bit by specifying the page address and the
column address. Since the display data D7 to D0 from the MPU correspond to the LCD display
inthedirectionofthecommonlinesasshowninFig. 3, therearefewerrestrictionsduringdisplay
data transfer when the ML9052 is used in a multiple chip configuration, thereby making it easily
possibletoimplementadisplaywithahighdegreeoffreedom. Also, sincethedisplaydataRAM
read/write from the MPU side is carried out via an I/O buffer, it is done independently of the
signal read operation for the LCD drive. Consequently, the display is not affected by flickering,
etc., even when the display data RAM is accessed asynchronously during the LCD display
operation.
D0
D1
D2
D3
D4
0 1 1 1 - - - 0
1 0 0 0 - - - 0
0 0 0 0 - - - 0
0 1 1 1 - - - 0
1 0 0 0 - - - 0
COM0
COM1
COM2
COM3
COM4
- - -
- - -
- - -
- - -
- - -
Display data RAM
LCD Display
Figure 3
• Page address circuit
The page address of the display data RAM is specified using the page address set command as
shown in Fig. 4. Specify the page address again when accessing after changing the page. The
page address 12 (D3, D2, D1, D0 Æ 1, 1, 0, 0) is the RAM area dedicated to the indicator, and only
the display data D0 is valid in this page.
• Column address circuit
ThecolumnaddressofthedisplaydataRAMisspecifiedusingthecolumnaddresssetcommand
asshowninFig.4. Sincethespecifiedcolumnaddressisincremented(by+1)everytimeadisplay
data read/write command is issued, the MPU can access the display data continuously. Further,
the incrementing of the column address is stopped at the column address of 83H. Since the
column address and the page address are independent of each other, it is necessary, for example,
to specify separately the new page address and the new column address when changing from
column83Hofpage0tocolumn00Hofpage1. Also,asisshowninTable4,itispossibletoreverse
the correspondence relationship between the display data RAM column address and the
segment output using the ADC command (the segment driver direction select command). This
reduces the IC placement restrictions at the time of assembling LCD modules.
Table 4
SEG Output
ADC
SEG0
SEG131
D0 = "0"
D0 = "1"
0(H) Æ Column Address Æ 83(H)
83(H) ¨ Column Address ¨ 0(H)
12/64
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