PEDL9050-02
ML9050/9051
¡ Semiconductor
Serial interface
Whentheserialinterfaceisselected(P/S="L"), theserialdatainput(SI)andtheserialclockinput
(SCL)canbeacceptedifthechipisintheactivestate(CS1="L"andCS2="H"). Theserialinterface
consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data
input pin in the sequence D7, D6, ... , D0 at the rising edge of the serial clock input, and is
converted into parallel data at the rising edge of the 8th serial clock pulse and processed further.
The identification of whether the serial data is display data or command is judged based on the
A0 input, and the data is treated as display data when A0 is "H" and as command when A0 is "L".
The A0 input is read in and identified at the rising edge of the (8 ¥ n) th serial clock pulse after
the chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip
is not active, the shift register and the counter are reset to their initial states. No data read out
is possible in the case of the serial interface. It is necessary to take sufficient care about wiring
termination reflection and external noise in the case of the SCL signal. We recommend
verification of operation in an actual unit.)
CS1
CS2
SI
SC
A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Fig. 1
• Chip select
The ML9050/9051 has the two chip select pins CS1 and CS2, and the MPU interface or the serial
interface is enabled only when CS1 = "L" and CS2 = "H". When the chip select signals are in the
inactive state, the D0 to D7 lines will be in the high impedance state and the inputs A0, RD, and
WR will not be effective. When the serial interface has been selected, the shift register and the
counter are reset when the chip select signals are in the inactive state.
• Accessing the display data RAM and the internal registers
Accessing the ML9050/9051 from the MPU side requires merely that the cycle time (t
) be
CYC
satisfied, and high speed data transfer without requiring any wait time is possible. Also, during
the data transfer with the MPU, the ML9050/9051 carries out a type of pipeline processing
betweenLSIsviaa busholder associatedwith theinternaldatabus. Forexample, when the MPU
writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then
written into the display data RAM before the next data read cycle. Further, when the MPU reads
outdatainthedisplaydataRAM,firstadummydatareadcycleiscarriedouttotemporarilystore
the data in the bus holder which is then placed on the system bus and is read out during the next
read cycle. There is a restriction on the read sequence of the display data RAM, which is that the
read instruction immediately after setting the address does not read out the data of that address,
but that data is output as the data of the address specified during the second data read sequence,
and hence care should be taken about this during reading. Therefore, always one dummy read
is necessary immediately after setting the address or after a write cycle. This relationship is
shown in Figs 2(a) and 2(b).
10/71
OKI [ OKI ELECTRONIC COMPONETS ]
