欢迎访问ic37.com |
会员登录 免费注册
发布采购

ML9042-01CVWA 参数 Datasheet PDF下载

ML9042-01CVWA图片预览
型号: ML9042-01CVWA
PDF下载: 下载PDF文件 查看货源
内容描述: [Dot Matrix LCD Driver, 17 X 100 Dots, CMOS, DIE-233]
分类和应用: 时钟驱动外围集成电路
文件页数/大小: 58 页 / 558 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
 浏览型号ML9042-01CVWA的Datasheet PDF文件第1页浏览型号ML9042-01CVWA的Datasheet PDF文件第2页浏览型号ML9042-01CVWA的Datasheet PDF文件第3页浏览型号ML9042-01CVWA的Datasheet PDF文件第5页浏览型号ML9042-01CVWA的Datasheet PDF文件第6页浏览型号ML9042-01CVWA的Datasheet PDF文件第7页浏览型号ML9042-01CVWA的Datasheet PDF文件第8页浏览型号ML9042-01CVWA的Datasheet PDF文件第9页  
FEDL9042-01  
OKI Semiconductor  
ML9042-xx  
PIN DESCRIPTIONS  
Symbol  
RW/SI  
Description  
The input pin with a pull-up resistor to select Read (“H”) or Write (“L”) in the Parallel I/F  
Mode.  
The pin to input data in the Serial l/F Mode. Each instruction code and each data are  
read in by the rising edge of the E/SHTB signal.  
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.  
RS1  
H
RS0/CSB  
Name of register  
Data register  
H
L
L
RS0/CSB, RS1  
H
Instruction register  
L
Expansion Instruction register  
The RSo/CSB pin is configured as a chip enable input in the Serial I/F Mode. Setting  
the RSo/CSB pin to “L” allows the I/F to be provided.  
The input pin for data input/output between the CPU and the ML9042 and for  
activating instructions in the Parallel l/F Mode.  
E/SHTB  
This pin is configured as a shift clock input in the Serial I/F Mode. The data input to the  
PW/SI pin is synchronized to the rising edge of the clock, and the data output from the  
DB0(SO) pin is synchronized to the falling edge of the shift clock.  
The input/output pins to transfer data of lower-order 4 bits between the CPU and the  
ML9042 in the Parallel l/F Mode. The pins are not used for the 4-bit interface.  
Only the DB0(SO) pin is configured as a data output in the Serial I/F Mode. Busy flag  
& address and data are output synchronized to the falling edge of the E/SHTB signal.  
These pins remain pulled up when data is not output.  
DB0(SO) to DB3  
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.  
The input/output pins to transfer data of upper 4 bits between the CPU and the  
ML9042 in the Parallel l/F Mode. The pins are not used for the serial interface.  
DB4 to DB7  
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F  
Mode when not used.  
The clock oscillation pins required for LCD drive signals and the operation of the  
ML9042 by instructions sent from the CPU.  
To input external clock, the OSC1 pin should be used. The OSCR3, OSCR5, and OSC2  
pins should be open.  
OSC1  
OSC2  
To start oscillation with an external resistor, the resistor should be connected between  
the OSC1 and OSC2 pins. The OSCR3 and OSCR5 pins should be open.  
OSCR3  
OSCR5  
To start oscillation at 5 V using an internal resistor, the OSC2 and OSCR5 pins should  
be short-circuited outside the ML9042. The OSC1 and OSCR3 pins should be open.  
To start oscillation at 3 V using an internal resistor, the OSC2 and OSCR3 pins should  
be short-circuited outside the ML9042. The OSC1 and OSCR5 pins should be open.  
(The OSC2, OSCR3, and OSCR5 pins can also be short-circuited outside the ML9042,  
and the OSC1 pin can be open.)  
The LCD common signal output pins.  
For 1/8 duty, non-selectable voltage waveforms are output via COM9 to COM17. For  
1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/16  
duty, a non-selectable voltage waveform is output via COM17.  
COM1 to COM17  
SEG1 to SEG100  
The LCD segment signal output pins.  
4/58