PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
DC Characteristics
(Ta = 0 to 70°C)
Parameter
H level input voltage
L level input voltage
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS, OVS, OHS,
RESET)
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS, OVS, OHS,
RESET)
Hysteresis voltage width
H level input current (pull-down)
Input leakage current
H level output voltage (other than SDA)
L level output voltage (other than SDA)
L level output voltage (N-Ch.OD)
(SDA)
Output leakage current
Symbol
V
IH
V
IL
V
t+
V
t–
V
h
I
IH
I
IL
V
OH
V
OL
V
OOL
I
OL
Condition
—
—
—
—
—
50 kΩ Pull Down
TTL
I
OH
= –4 mA
I
OL
= 4 mA
I
OL
= 4 mA
0
≤
V
out
≤
V
DD
Output disabled
ICLK: 29.5 MHz
OCLK: 29.5 MHz
Output disabled
Input pin = V
IL
Min.
2.0
–0.3
—
0.8
0.1
20
–10
2.4
0
0
–10
Max.
5.5
0.8
2.0
—
—
200
10
V
DD
0.4
0.4
10
Unit
V
V
V
V
V
µA
µA
V
V
V
µA
Supply current (during operation)
Supply current (during standby)
I
DD1
I
DD2
—
—
120
5
mA
mA
AC Characteristics
(Ta = 0 to 70°C)
Parameter
ICLK clock cycle time
ICLK clock duty ratio
ICLK system input set-up time
ICLK system input hold time
OCLK clock cycle time
OCLK clock duty ratio
OCLK system input set-up time
OCLK system input hold time
OCLK system output delay time
CLKO delay time
Data through time
Symbol
t
ICLK
dt
ICLK
t
IISU
t
IIH
t
OCLK
dt
OCLK
t
OISU
t
OIH
t
OOD
t
CKD
t
DIDO
Condition
—
—
—
—
—
—
—
—
C
L
= 30 pF
C
L
= 30 pF
C
L
= 20 pF
Min.
33
40
5
3
33
40
5
3
5
4
5
Max.
—
60
—
—
—
60
—
—
25
20
20
Unit
ns
%
ns
ns
ns
%
ns
ns
ns
ns
ns
*1: ( ) indicates the input internal system clock cycle.
Note 1: Measurement conditions
Output comparison level: V
OH
= 1.5 V, V
OL
= 1.5 V
Input voltage level: V
IH
= 3.0 V, V
IL
= 0.0 V
Note 2: .When writing input data to the memory, compensation is applied from the second input system
vertical synchronization signal when V
DD
reaches 3.0 V after the power is turned on, and when
RESET
= 1. (Due to memory initialization, the first data for the first field is not compensated.)
Note 3: .When reading output data from the memory, compensation is applied from the second output
system vertical synchronization signal when V
DD
reaches 3.0 V after the power is turned on, and
when
RESET
= 1. (Due to memory initialization, the first data for the first field is not compensated.)
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