FEDL87V3104-03
OKI Semiconductor
ML87V3104
PIN DESCRIPTIONS
Table P1. List of pins and their descriptions
Pin
Symbol
I/O
Type
27
28
29
30
32-35
37
38
42-45
47-50
52-55
59, 60
62, 64, 65
66, 67, 70, 71
73, 74, 76-79
81-84, 86, 87
92-95, 97-100
2
3
4
5
7
8
10
9
12
14
16
18, 19, 21, 22
23, 24
58
11, 20, 61, 68,
85, 96
36, 46
6, 15, 31, 40,
56, 63, 80, 88
DISP
DF
FRP
LCP
DDA3 - 0
CPS
CP
DDB3 - 0
DDC3 - 0
DDD3 - 0
PORT0, 1
A18 - 16
AD15 - 00
O
O
O
O
O
O
O
O
O
O
I/O
I
I/O
4mA drive
4mA drive
4mA drive
4mA drive
4mA drive
3-state
4mA drive
4mA drive
4mA drive
3-state
4mA drive
3-state
4mA drive
3-state
LVTTL /
4mA drive
LVTTL
LVTTL /
4mA drive
LVTTL /
4mA drive
LVTTL, Schmitt
LVTTL, Schmitt
LVTTL, Schmitt
LVTTL, Schmitt
LVTTL, Schmitt
8mA drive
3-state
LVTTL, Schmitt
LVTTL, Schmitt
X’tal oscillation
buffer
LVTTL
LVTTL
LVTTL
2mA drive
Power Supply
Power Supply
Power Supply
Description
LCD Display enable
LCD AC driving signal pin
LCD Frame pulse
LCD Line clock pulse
LCD Data A
LCD Data clock pulse 2 or Data Strobe
LCD Data clock pulse
LCD Data B
LCD Data C
LCD Data D
General purpose I/O port (input / output direction
can be set for each pin)
Host address bus
Host address/data multiplexed bus
D07 - 00
CSN
REN
WEN
BSN
DSN
BSYN
BCLK
REGS
XOSCI
XOSCO
RESETN
HMOD3 - 0
TEST1, 0
(TOUT)
VDDI
VDDO
VSS
I/O
I
I
I
I
I
O
I
I
I
O
I
I
I
O
—
—
—
Host data bus
Chip select (active “L”)
Read enable (active “L”)
Write enable (active “L”)
Bus start/address strobe (active “L”)
Data strobe (active “L”)
Busy/wait (active “L”, 3-stated)
Bus clock
Register select
Clock oscillator input (built-in feedback resistor)
Clock oscillator output
System reset (active “L”)
Host mode select
Test mode select (normally tied to “L”)
(Test output. Not used.)
Power supply for the internal core and I/O
Power supply for the LCD interface signal outputs
Common ground
4/69
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