PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
PIN DESCRIPTIONS
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Symbol
N.C.
V
SS
SDA
SCL
SLA1
SLA2
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
V
DD
ICLK
V
SS
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
V
DD
N.C.
V
SS
IVS
IHS
MODE0
MODE1
N.C.
MODE2
CLKO
V
DD
V
SS
N.C.
N.C.
I/O
—
—
I/O
I
I
I
I
I
I
I
I
I
I
I
—
I
—
I
I
I
I
I
I
I
I
—
—
—
I
I
I
Pad Remarks
Unused pin
Ground
Schmitt(IN)/
OpenDrain(OUT)
Schmitt
Internal pull-down 50k
Internal pull-down 50k
I
2
C-bus data pin
I
2
C-bus clock pin
Slave address setting pin
Slave address setting pin
Luminance signal input pin bit 7 (MSB)
Luminance signal input pin bit 6
Luminance signal input pin bit 5
Luminance signal input pin bit 4
Luminance signal input pin bit 3
Luminance signal input pin bit 2
Luminance signal input pin bit 1
Luminance signal input pin bit 0 (LSB)
Power supply 3.3 V
Input system clock pin
Ground
Color difference signal input pin bit 7 (MSB)
Color difference signal input pin bit 6
Color difference signal input pin bit 5
Color difference signal input pin bit 4
Color difference signal input pin bit 3
Color difference signal input pin bit 2
Color difference signal input pin bit 1
Color difference signal input pin bit 0 (LSB)
Power supply 3.3 V
Unused pin
Ground
Pin Description
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Schmitt
Input system vertical sync signal input pin
Internal pull-down 50k
Schmitt
Input system horizontal sync signal input pin
Internal pull-down 50k
Internal pull-down 50k Mode setting pin – bit 0
Mode setting pin – bit 1
Unused pin
Mode setting pin – bit 2
Clock output (I
2
C-bus control possible)
Power supply 3.3 V
Ground
Unused pin
Unused pin
I Internal pull-down 50k
—
I Internal pull-down 50k
O/(I)
—
—
—
—
4/14
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