PEDL86V7668-01
OKI Semiconductor
ML86V7668
Pin
44
Symbol
PLLSEL
I/O
I
Description
System clock select pin.
“0”: Fixed clock, “1”: PLL reference clock
45
DVDDCO
Digital power supply
System clock input, or PLL reference clock input (Pin 44 = “0”)
NTSC ITU-R BT.601
NTSC Square Pixel
PAL ITU-R BT.601
27 MHz
24.545454 MHz
27 MHz
46
CLKX2
I
SECAM ITU-R BT.601 27 MHz
PLL reference clock (Pin 44 = “1”)
Register $70/PLLC1[6] “0”: 32 MHz*, “1”: 25 MHz
47
48
49
50
51
DGNDCO
HSYNC_L
VSYNC_L
DVDDIO
Digital core ground
O
O
Horizontal sync signal output (H sync)
Vertical sync signal output (V sync)
Digital IO power supply
Digital IO ground
DGNDIO
Data output
C[7]:MSB - C[0]
ITU-R BT.656 mode
: Hi-Z
52
|
59
C [0]
|
C [7]
8-bit Y/CbCr mode
16-bit Y/CbCr mode
18-bit RGB mode
: Hi-Z
O
: 8-bit (CbCr)data output
: C[7:6] = G[1:0]
: C[5:0] = R[5:0]
The output mode is set by pins 30 and 31, or register $01/IOC2[5:4].
60
61
DGNDCO
CLKX2O
Digital core ground
System clock output
The system clock is output from this pin.
The system clock in operation mode is output when PLL clock mode is
O
used.
Pixel clock output
62
63
CLKXO
O
The pixel frequency is output.
(1/2 frequency of the system clock)
DGNDCO
Digital core ground
Data output Y[7]:MSB - Y[0]
ITU-R BT.656 mode
: YCbCr 8-bit data output
: YCbCr 8-bit data output
: 8-bit(Y) data output
: Y[7:4]=B[3:0]
64
|
71
Y [0]
|
Y [7]
8-bit Y/CbCr mode
16-bit Y/CbCr mode
18-bit RGB mode
O
: Y[3:0]=G[5:2]
The output mode is set by pins 30 and 31, or register $01/IOC2[5:4].
7/31
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