PEDL86V7667-00
OKI Semiconductor
ML86V7667
PIN DESCRIPTIONS
Pin
1
2
3
Symbol
PVDD
VREF
LPF
I/O
O
I
Description
PLL power supply
Center frequency setting pin. Connect to the PGND pin when not
used.
Analog PLL loop filter connection pin. Connect to the PGND pin
when not used.
See the sample circuit provided in the User's Manual.
PLL ground
Digital power supply in the analog block.
Digital ground in the analog block.
Analog ground
Composite-1 input
Connect this pin to AGND when not used.
Composite-2 input
Connect this pin to AGND when not used.
Analog power supply
A/D C reference voltage (high)
Should be left pen.
A/D C reference voltage (middle)
Should be left pen.
A/D C reference voltage (low)
Should be left pen.
Analog ground
Not used. Open
Analog power supply
Digital power supply
Digital ground
Not used. Should be fixed to "0".
Sleep signal input.
“0”:
Normal operation,
“1”:
Sleep operation
Reset signal input.
“0”:
Reset, 1: Normal operation
Reset after power ON.
Not used. Should be fixed to "0".
Not used. Should be fixed to "0".
Not used. Should be fixed to "0".
I
2
C bus data input/output pin. Pulled up by a 4.7 k resistor.
Putt this pin into the
“0”
state when not used.
2
I C bus clock input. Put this pin into the
“0”
state when not used.
STATUS output pin 1. Selected by the internal register.
Default HVALID
STATUS output pin 2. Selected by the internal register.
Default VVALID
STATUS output pin 3. Selected by the internal register.
Default ODD/EVEN
STATUS output pin 4. Selected by the internal register.
Default CSYNC
4
5
6
７
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PGND
ADVDD
ADGND
AGND
VIN1
VIN2
AVDD
REFP
CM
REFN
AGND
LPFOUT
AVDD
DVDD
DGND
SCAN
SLEEP
RESET_L
TEST [2]
TEST [1]
TEST [0]
SDA
SCL
STATUS1
STATUS2
STATUS3
STATUS4
I
I
O
O
O
O
I
I
I
I
I
I
I/O
I
O
O
O
O
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OKI [ OKI ELECTRONIC COMPONETS ]
