FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
PIN DESCRIPTIONS
Pin
No.
1
2
3
4
5
Symbol
TST1
TST0
PCMO
PCMI
BCLK
I/O PDNB = “0”
I
I
O
I
I/O
“L”
I
6
7
8
9
10
SYNC
DV
DD
0
ACK0B
ACK1B
FR0B
(DMARQ0B)
I/O
“L”
I
I
O
I
I
”H”
“0”
“0”
“Hi-z”
I
I
Description
Test control input 1: Normally input “0”.
Test control input 0: Normally input “0”.
PCM data output
PCM data input
CLKSEL = ”0”
PCM shift clock input
CLKSEL = ”1”
PCM shift clock output
CLKSEL = ”0”
PCM sync signal 8 kHz input
CLKSEL = ”1”
PCM sync signal 8 kHz output
Digital power supply
Transmit buffer DMA access acknowledge signal input
Receive buffer DMA access acknowledge signal input
FR0B: (CR11-B7 = ”0”)
Transmit buffer frame signal output
DMARQ0B: (CR11-B7 = ”1”)
Transmit buffer DMA access request signal output
FR1B: (CR11-B7 = ”0”)
Receive buffer frame signal output
DMARQ1B: (CR11-B7 = ”1”)
Receive buffer DMA access request signal output
Interrupt request output
“L” level is output for about 1.0
µsec
when an interrupt is generated.
Chip select control input
Read control input
Write control input
Digital ground (0.0 V)
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
11
FR1B
(DMARQ1B)
INTB
CSB
RDB
WRB
DGND0
D0
D1
D2
D3
D4
D5
D6
D7
D8
O
“H”
12
13
14
15
16
17
18
19
20
21
22
23
24
25
O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
“H”
I
I
I
I
I
I
I
I
I
I
I
I
I
4/31
OKI [ OKI ELECTRONIC COMPONETS ]
